From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD495C77B7A for ; Thu, 1 Jun 2023 16:08:09 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id E20EFE74; Thu, 1 Jun 2023 18:07:17 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz E20EFE74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1685635688; bh=uxFTaoefzGrlQJwPOsKt/Oa3fwM4sNdI6lUBM40SeDc=; h=Date:Subject:To:CC:References:From:In-Reply-To:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; 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Wed, 31 May 2023 14:23:54 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 31 May 2023 14:23:54 +0800 Received: from [192.168.125.80] (113.72.147.198) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 31 May 2023 14:23:53 +0800 Message-ID: Date: Wed, 31 May 2023 14:23:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH v5 3/3] riscv: dts: starfive: add the node and pins configuration for tdm To: Walker Chen , Mark Brown , Liam Girdwood , Claudiu Beznea , Jaroslav Kysela , "Takashi Iwai" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Emil Renner Berthing" CC: , , , References: <20230526145402.450-1-walker.chen@starfivetech.com> <20230526145402.450-4-walker.chen@starfivetech.com> Content-Language: en-US From: Hal Feng In-Reply-To: <20230526145402.450-4-walker.chen@starfivetech.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [113.72.147.198] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag X-MailFrom: hal.feng@starfivetech.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: 7463NWR3XTQ4CYYFPTTLGF4LFS5U6RMF X-Message-ID-Hash: 7463NWR3XTQ4CYYFPTTLGF4LFS5U6RMF X-Mailman-Approved-At: Thu, 01 Jun 2023 16:02:28 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: <> List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On Fri, 26 May 2023 22:54:02 +0800, Walker Chen wrote: > Add the tdm controller node and pins configuration of tdm for the > StarFive JH7110 SoC. > > Signed-off-by: Walker Chen > --- > .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ > 2 files changed, 61 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 1155b97b593d..19b5954ee72d 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -214,6 +214,40 @@ > slew-rate = <0>; > }; > }; > + > + tdm0_pins: tdm0-pins { > + tdm0-pins-tx { Use consistent naming, so tdm_pins: tdm-0 { tx-pins { > + pinmux = + GPOEN_ENABLE, > + GPI_NONE)>; > + bias-pull-up; > + drive-strength = <2>; > + input-disable; > + input-schmitt-disable; > + slew-rate = <0>; > + }; > + > + tdm0-pins-rx { rx-pins { > + pinmux = + GPOEN_DISABLE, > + GPI_SYS_TDM_RXD)>; > + input-enable; > + }; > + > + tdm0-pins-sync { sync-pins { > + pinmux = + GPOEN_DISABLE, > + GPI_SYS_TDM_SYNC)>; > + input-enable; > + }; > + > + tdm0-pins-pcmclk { pcmclk-pins { > + pinmux = + GPOEN_DISABLE, > + GPI_SYS_TDM_CLK)>; > + input-enable; > + }; > + }; > }; > > &uart0 { > @@ -221,3 +255,9 @@ > pinctrl-0 = <&uart0_pins>; > status = "okay"; > }; > + > +&tdm { > + pinctrl-names = "default"; > + pinctrl-0 = <&tdm0_pins>; pinctrl-0 = <&tdm_pins>; Best regards, Hal > + status = "okay"; > +};