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Tue, 5 Sep 2023 21:25:48 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by anon-ediex02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server id 15.2.1118.37 via Frontend Transport; Tue, 5 Sep 2023 21:25:48 +0100 Received: from [141.131.157.8] (macMW3KVPQQ2W.ad.cirrus.com [141.131.157.8]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id DB49746B; Tue, 5 Sep 2023 20:25:46 +0000 (UTC) Message-ID: Date: Tue, 5 Sep 2023 15:25:46 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.14.0 Subject: Re: [PATCH 4/9] ASoC: cs35l41: Fix broken shared boost activation Content-Language: en-US To: Cristian Ciocaltea , Charles Keepax CC: James Schulman , David Rhodes , Richard Fitzgerald , Jaroslav Kysela , Takashi Iwai , "Liam Girdwood" , Mark Brown , "Stefan Binding" , , , , References: <20230902210621.1184693-1-cristian.ciocaltea@collabora.com> <20230902210621.1184693-5-cristian.ciocaltea@collabora.com> <20230905102933.GL103419@ediswmail.ad.cirrus.com> <1cd66d6d-6a39-41eb-8646-0a6e6f473e8d@collabora.com> From: "Rhodes, David" In-Reply-To: <1cd66d6d-6a39-41eb-8646-0a6e6f473e8d@collabora.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: fbPf4wxmXlYDfcSCXGGmXTH1--H0fzrp X-Proofpoint-GUID: fbPf4wxmXlYDfcSCXGGmXTH1--H0fzrp X-Proofpoint-Spam-Reason: safe Message-ID-Hash: 23IUKDBMEXV3QMAKIODECL6MTAWSWPIV X-Message-ID-Hash: 23IUKDBMEXV3QMAKIODECL6MTAWSWPIV X-MailFrom: prvs=4612ed829b=drhodes@opensource.cirrus.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: On 9/5/23 3:05 PM, Cristian Ciocaltea wrote: > If I got it right, we should drop all write operations on PWR_CTRL1, > and simply set the CS35L41_SYNC_EN_MASK bit in PWR_CTRL3. > That's a good point, it should be fixed implicitly by replacing the > read/write operations with a single regmap_update_bits() call, which > is protected by regmap's internal lock. > Yes, my recommendation is to replace the mdsync_up_sequence and completion handling with a single regmap_update_bits() call to set the CS35L41_SYNC_EN_MASK bit in PWR_CTRL3, which occurs in response to the PLL Lock interrupt. Thanks, David