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[92.40.203.179]) by smtp.gmail.com with ESMTPSA id p15-20020a05600c204f00b0039c5cecf206sm28717513wmg.4.2022.07.07.07.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 07:23:44 -0700 (PDT) References: <20220706211330.120198-1-aidanmacdonald.0x0@gmail.com> <20220706211330.120198-10-aidanmacdonald.0x0@gmail.com> From: Aidan MacDonald To: Paul Cercueil Subject: Re: [PATCH 09/11] ASoC: jz4740-i2s: Make the PLL clock name SoC-specific In-reply-to: Date: Thu, 07 Jul 2022 15:24:52 +0100 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Cc: alsa-devel@alsa-project.org, lgirdwood@gmail.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, tiwai@suse.com, broonie@kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Paul Cercueil writes: > Le mer., juil. 6 2022 at 22:13:28 +0100, Aidan MacDonald > a =C3=A9crit : >> On some Ingenic SoCs, such as the X1000, there is a programmable >> divider used to generate the I2S system clock from a PLL, rather >> than a fixed PLL/2 clock. It doesn't make much sense to call the >> clock "pll half" on those SoCs, so the clock name should really be >> a SoC-dependent value. > > Do you really need the .set_sysclk() callback? I've never seen it used on= any > of the Ingenic boards I have, so to me it's pretty much dead code. Unless= you > do use this callback, I'd suggest to drop this patch until you do need it. > > Cheers, > -Paul > Yes, one of my boards has an external codec (AK4376) that needs the sysclock and I've patched simple-card to be able to set a non-zero sysclock ID. >> Signed-off-by: Aidan MacDonald >> --- >> sound/soc/jz4740/jz4740-i2s.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s= .c >> index 3a21ee9d34d1..80b355d715ce 100644 >> --- a/sound/soc/jz4740/jz4740-i2s.c >> +++ b/sound/soc/jz4740/jz4740-i2s.c >> @@ -71,6 +71,8 @@ struct i2s_soc_info { >> struct reg_field field_tx_fifo_thresh; >> struct reg_field field_i2sdiv_capture; >> struct reg_field field_i2sdiv_playback; >> + >> + const char *pll_clk_name; >> }; >> struct jz4740_i2s { >> @@ -265,7 +267,7 @@ static int jz4740_i2s_set_sysclk(struct snd_soc_dai = *dai, >> int clk_id, >> clk_set_parent(i2s->clk_i2s, parent); >> break; >> case JZ4740_I2S_CLKSRC_PLL: >> - parent =3D clk_get(NULL, "pll half"); >> + parent =3D clk_get(NULL, i2s->soc_info->pll_clk_name); >> if (IS_ERR(parent)) >> return PTR_ERR(parent); >> clk_set_parent(i2s->clk_i2s, parent); >> @@ -387,6 +389,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_info= =3D { >> .field_tx_fifo_thresh =3D REG_FIELD(JZ_REG_AIC_CONF, 8, 11), >> .field_i2sdiv_capture =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name =3D "pll half", >> }; >> static const struct i2s_soc_info jz4760_i2s_soc_info =3D { >> @@ -395,6 +398,7 @@ static const struct i2s_soc_info jz4760_i2s_soc_info= =3D { >> .field_tx_fifo_thresh =3D REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> .field_i2sdiv_playback =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name =3D "pll half", >> }; >> static struct snd_soc_dai_driver jz4770_i2s_dai =3D { >> @@ -421,6 +425,7 @@ static const struct i2s_soc_info jz4770_i2s_soc_info= =3D { >> .field_tx_fifo_thresh =3D REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name =3D "pll half", >> }; >> static const struct i2s_soc_info jz4780_i2s_soc_info =3D { >> @@ -429,6 +434,7 @@ static const struct i2s_soc_info jz4780_i2s_soc_info= =3D { >> .field_tx_fifo_thresh =3D REG_FIELD(JZ_REG_AIC_CONF, 16, 20), >> .field_i2sdiv_capture =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 8, 11), >> .field_i2sdiv_playback =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3), >> + .pll_clk_name =3D "pll half", >> }; >> static const struct snd_soc_component_driver jz4740_i2s_component =3D { >> -- >> 2.35.1 >>=20