From mboxrd@z Thu Jan 1 00:00:00 1970 From: Takashi Iwai Subject: Re: [PATCH] ASoC: fsl: Correct FSL_SAI_CR2_MSEL_MASK definition Date: Wed, 03 Jun 2015 21:29:42 +0200 Message-ID: References: <1433335861-31474-1-git-send-email-tiwai@suse.de> <20150603184714.GA8196@Asurada> Mime-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mx2.suse.de (cantor2.suse.de [195.135.220.15]) by alsa0.perex.cz (Postfix) with ESMTP id 7F8CB2606FD for ; Wed, 3 Jun 2015 21:29:44 +0200 (CEST) In-Reply-To: <20150603184714.GA8196@Asurada> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Nicolin Chen Cc: Xiubo Li , alsa-devel@alsa-project.org, Mark Brown , Liam Girdwood , Timur Tabi List-Id: alsa-devel@alsa-project.org At Wed, 3 Jun 2015 11:47:15 -0700, Nicolin Chen wrote: > > Hello Iwai-san, > > On Wed, Jun 03, 2015 at 02:51:01PM +0200, Takashi Iwai wrote: > > The bit mask FSL_SAI_CR2_MSEL_MASK is defined as (0xff << 26) and this > > obviously overflows the 32bit integer. Also this clears other bits > > than the needed ones (FSL_SAI_CR2_MSEL_XXX) wrongly. > > > > This patch fixes the definition only to mask bits 26 and 27. > > An identical fix was included in the Commit c3ecef21c3f26bf47 > (ASoC: fsl_sai: add sai master mode support) by Zidan Wang. > And it's already in the linux-next tree. Ah good, thanks. I hope I would have received pulls for ASoC changes more often... Takashi > > Thank you > Nicolin > > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=84351 > > Reported-by: David Binderman > > Signed-off-by: Takashi Iwai > > --- > > sound/soc/fsl/fsl_sai.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > > index 34667209b607..0e33a17ddd01 100644 > > --- a/sound/soc/fsl/fsl_sai.h > > +++ b/sound/soc/fsl/fsl_sai.h > > @@ -72,7 +72,7 @@ > > > > /* SAI Transmit and Recieve Configuration 2 Register */ > > #define FSL_SAI_CR2_SYNC BIT(30) > > -#define FSL_SAI_CR2_MSEL_MASK (0xff << 26) > > +#define FSL_SAI_CR2_MSEL_MASK (0x03 << 26) > > #define FSL_SAI_CR2_MSEL_BUS 0 > > #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) > > #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) > > -- > > 2.4.2 > > >