From mboxrd@z Thu Jan 1 00:00:00 1970 From: Takashi Iwai Subject: Re: [RFC PATCH] ALSA: hda - reset hda link during system/runtime suspend Date: Mon, 24 Jun 2013 09:44:12 +0200 Message-ID: References: <1372083534-9706-1-git-send-email-mengdong.lin@intel.com> Mime-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mx2.suse.de (cantor2.suse.de [195.135.220.15]) by alsa0.perex.cz (Postfix) with ESMTP id 47A10261A66 for ; Mon, 24 Jun 2013 09:43:19 +0200 (CEST) In-Reply-To: <1372083534-9706-1-git-send-email-mengdong.lin@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: mengdong.lin@intel.com Cc: pshou@realtek.com, alsa-devel@alsa-project.org, kailang@realtek.com List-Id: alsa-devel@alsa-project.org At Mon, 24 Jun 2013 10:18:54 -0400, mengdong.lin@intel.com wrote: > > From: Mengdong Lin > > If all the codecs report ClkStopOK (OK to stop bus clock) after being put to > D3, this patch will reset the HDA link before the controller is put to D3. > > So the link will be in reset during system or runtime suspend, the bus clock > stops and the codecs are in D3(ClkStop) state. > > This may help to reduce power consumption by dozens of mW on some peripheral > hda codecs. Do you have the actually measured result, or is it just a hypothesis? The patch looks safe, so I'm going to apply it, but would like to know the influence. thanks, Takashi > > Signed-off-by: Mengdong Lin > > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c > index f089fa0..9f110c7 100644 > --- a/sound/pci/hda/hda_intel.c > +++ b/sound/pci/hda/hda_intel.c > @@ -1120,6 +1120,20 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus, > struct snd_dma_buffer *dmab); > #endif > > +/* enter link reset */ > +static void azx_reset_link(struct azx *chip) > +{ > + unsigned long timeout; > + > + /* reset controller */ > + azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); > + > + timeout = jiffies + msecs_to_jiffies(100); > + while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && > + time_before(jiffies, timeout)) > + usleep_range(500, 1000); > +} > + > /* reset codec link */ > static int azx_reset(struct azx *chip, int full_reset) > { > @@ -2894,6 +2908,7 @@ static int azx_suspend(struct device *dev) > if (chip->initialized) > snd_hda_suspend(chip->bus); > azx_stop_chip(chip); > + azx_reset_link(chip); > if (chip->irq >= 0) { > free_irq(chip->irq, chip); > chip->irq = -1; > @@ -2946,6 +2961,7 @@ static int azx_runtime_suspend(struct device *dev) > struct azx *chip = card->private_data; > > azx_stop_chip(chip); > + azx_reset_link(chip); > azx_clear_irq_pending(chip); > return 0; > } > -- > 1.7.10.4 >