From mboxrd@z Thu Jan 1 00:00:00 1970 From: Takashi Iwai Subject: Re: [PATCH 1/2] ASoC: Add support for Conexant CX2072X CODEC Date: Thu, 02 May 2019 09:52:40 +0200 Message-ID: References: <20190423141336.12568-1-tiwai@suse.de> <20190423141336.12568-2-tiwai@suse.de> <20190427175938.GJ14916@sirena.org.uk> Mime-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mx1.suse.de (mx2.suse.de [195.135.220.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id E1B29F89693 for ; Thu, 2 May 2019 09:52:41 +0200 (CEST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" To: Mark Brown Cc: alsa-devel@alsa-project.org, Pierre-Louis Bossart List-Id: alsa-devel@alsa-project.org On Thu, 02 May 2019 09:04:06 +0200, Takashi Iwai wrote: > > > > +int snd_soc_cx2072x_get_jack_state(struct snd_soc_component *codec) > > > +{ > > > + struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec); > > > + unsigned int jack; > > > + unsigned int type = 0; > > > + int state = 0; > > > + bool need_cache_bypass = > > > + snd_soc_component_get_bias_level(codec) == SND_SOC_BIAS_OFF; > > > + > > > + if (need_cache_bypass) > > > + regcache_cache_only(cx2072x->regmap, false); > > > > This looks funky and racy - what's going on here? If the register map > > is live and usable why is it in cache only mode? > > Not to read the register while the chip is turned off, I suppose. Actually other way round: the codec driver tries to avoid the whole register access while the chip is in BIAS_OFF state. OTOH, the jack state check is still required even in that state, so it flips the cache-only flag temporarily at reading the jack detect bit. I guess we may remove the cache-only behavior, although this is a nice-to-have thing. Takashi