[PATCH v12] Add CRIU support for amdgpu dmabuf

[PATCH v12] Add CRIU support for amdgpu dmabuf

[David Francis]

This patch series adds support for CRIU checkpointing of processes that
share memory with the amdgpu dmabuf interface.

This v12 fixes some code path and code standard identified by Christian

Accompanying CRIU changes:
https://github.com/checkpoint-restore/criu/pull/2613

[PATCH v12 1/3] drm/amdgpu: Add ioctl to get all gem handles for a process

[David Francis]

Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES.

This ioctl returns a list of bos with their handles, sizes,
and flags and domains.

This ioctl is meant to be used during CRIU checkpoint and
provide information needed to reconstruct the bos
in CRIU restore.

Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 83 +++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h |  2 +
 include/uapi/drm/amdgpu_drm.h           | 31 +++++++++
 4 files changed, 117 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4ff3a2eaaf55..f19795dddf9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -3031,6 +3031,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
 	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 
 static const struct drm_driver amdgpu_kms_driver = {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index e3f65977eeee..3873d2c19b4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -1032,6 +1032,89 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 	return r;
 }
 
+/**
+ * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
+ *
+ * @dev: drm device pointer
+ * @data: drm_amdgpu_gem_list_handles
+ * @filp: drm file pointer
+ *
+ * num_bos is set as an input to the size of the bo_buckets array.
+ * num_bos is sent back as output as the number of bos in the process.
+ * If that number is larger than the size of the array, the ioctl must
+ * be retried.
+ *
+ * Returns:
+ * 0 for success, -errno for errors.
+ */
+int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *filp)
+{
+	struct drm_amdgpu_gem_list_handles *args = data;
+	struct drm_amdgpu_gem_list_handles_entry *bo_entries;
+	struct drm_gem_object *gobj;
+	int id, ret = 0;
+	int bo_index = 0;
+	int num_bos = 0;
+
+	spin_lock(&filp->table_lock);
+	idr_for_each_entry(&filp->object_idr, gobj, id)
+		num_bos += 1;
+	spin_unlock(&filp->table_lock);
+
+	if (args->num_entries < num_bos) {
+		args->num_entries = num_bos;
+		return 0;
+	}
+
+	if (num_bos == 0) {
+		args->num_entries = 0;
+		return 0;
+	}
+
+	bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
+	if (!bo_entries)
+		return -ENOMEM;
+
+	spin_lock(&filp->table_lock);
+	idr_for_each_entry(&filp->object_idr, gobj, id) {
+		struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
+		struct drm_amdgpu_gem_list_handles_entry *bo_entry;
+
+		if (bo_index >= num_bos) {
+			ret = -EAGAIN;
+			break;
+		}
+
+		bo_entry = &bo_entries[bo_index];
+
+		bo_entry->size = amdgpu_bo_size(bo);
+		bo_entry->alloc_flags = bo->flags & (~AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE);
+		/* WIPE_ON_RELEASE is set automatically in the driver; it is not permitted in
+		 * BO creation. In the interest of giving the user exactly the flags they need
+		 * to recreate the BO, clear it.
+		 */
+		bo_entry->preferred_domains = bo->preferred_domains;
+		bo_entry->gem_handle = id;
+
+		if (bo->tbo.base.import_attach)
+			bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
+
+		bo_index += 1;
+	}
+	spin_unlock(&filp->table_lock);
+
+	args->num_entries = bo_index;
+
+	if (!ret)
+		ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries));
+
+	kvfree(bo_entries);
+
+	return ret;
+}
+
+
 static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 				  int width,
 				  int cpp,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
index b51e8f95ee86..7cdb6237bb92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
@@ -67,6 +67,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *filp);
 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *filp);
+int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *filp);
 
 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
 				struct drm_file *filp);
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index bdedbaccf776..59b423883e91 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -57,6 +57,7 @@ extern "C" {
 #define DRM_AMDGPU_USERQ		0x16
 #define DRM_AMDGPU_USERQ_SIGNAL		0x17
 #define DRM_AMDGPU_USERQ_WAIT		0x18
+#define DRM_AMDGPU_GEM_LIST_HANDLES	0x19
 
 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -77,6 +78,7 @@ extern "C" {
 #define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
 #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
 #define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
+#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
 
 /**
  * DOC: memory domains
@@ -811,6 +813,35 @@ struct drm_amdgpu_gem_op {
 	__u64	value;
 };
 
+#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT	(1 << 0)
+
+struct drm_amdgpu_gem_list_handles {
+	/* User pointer to array of drm_amdgpu_gem_bo_info_entry */
+	__u64   entries;
+
+	/* IN: Size of entries buffer. OUT: Number of handles in process (if larger than size of buffer, must retry) */
+	__u32   num_entries;
+
+	__u32 padding;
+};
+
+struct drm_amdgpu_gem_list_handles_entry {
+	/* gem handle of buffer object */
+	__u32 gem_handle;
+
+	/* Currently just one flag: IS_IMPORT */
+	__u32 flags;
+
+	/* Size of bo */
+	__u64 size;
+
+	/* Preferred domains for GEM_CREATE */
+	__u64 preferred_domains;
+
+	/* GEM_CREATE flags for re-creation of buffer */
+	__u64 alloc_flags;
+};
+
 #define AMDGPU_VA_OP_MAP			1
 #define AMDGPU_VA_OP_UNMAP			2
 #define AMDGPU_VA_OP_CLEAR			3
-- 
2.34.1

[PATCH v12 2/3] drm/amdgpu: Add mapping info option for GEM_OP ioctl

[David Francis]

Add new GEM_OP_IOCTL option GET_MAPPING_INFO, which
returns a list of mappings associated with a given bo, along with
their positions and offsets.

Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  5 ++
 include/uapi/drm/amdgpu_drm.h           | 18 ++++++
 3 files changed, 108 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 3873d2c19b4b..1632460623b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -885,7 +885,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 				goto error;
 		}
 
-		r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
+		r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0);
 		drm_exec_retry_on_contention(&exec);
 		if (unlikely(r))
 			goto error;
@@ -956,6 +956,86 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 	return r;
 }
 
+/**
+ * amdgpu_gem_list_mappings - get information about a buffer's mappings
+ *
+ * @gobj: gem object
+ * @args: gem_op arguments
+ * @fpriv: drm file pointer
+ *
+ * num_entries is set as an input to the size of the user-allocated array of
+ * drm_amdgpu_gem_vm_bucket stored at args->value.
+ * num_entries is sent back as output as the number of mappings the bo has.
+ * If that number is larger than the size of the array, the ioctl must
+ * be retried.
+ *
+ * Returns:
+ * 0 for success, -errno for errors.
+ */
+static int amdgpu_gem_list_mappings(struct drm_gem_object *gobj, struct amdgpu_fpriv *fpriv,
+					  struct drm_amdgpu_gem_op *args)
+{
+	struct amdgpu_vm *avm = &fpriv->vm;
+	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
+	struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(avm, bo);
+	struct drm_amdgpu_gem_vm_bucket *vm_buckets;
+	struct amdgpu_bo_va_mapping *mapping;
+	struct drm_exec exec;
+	int num_mappings = 0;
+	int ret;
+
+	vm_buckets = kvcalloc(args->num_entries, sizeof(*vm_buckets), GFP_KERNEL);
+	if (!vm_buckets)
+		return -ENOMEM;
+
+	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
+			  DRM_EXEC_IGNORE_DUPLICATES, 0);
+	drm_exec_until_all_locked(&exec) {
+		if (gobj) {
+			ret = drm_exec_lock_obj(&exec, gobj);
+			drm_exec_retry_on_contention(&exec);
+			if (ret)
+				goto unlock_exec;
+		}
+
+		ret = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
+		drm_exec_retry_on_contention(&exec);
+		if (ret)
+			goto unlock_exec;
+	}
+
+	amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {
+		if (num_mappings < args->num_entries) {
+			vm_buckets[num_mappings].start = mapping->start;
+			vm_buckets[num_mappings].last = mapping->last;
+			vm_buckets[num_mappings].offset = mapping->offset;
+			vm_buckets[num_mappings].flags = mapping->flags;
+		}
+		num_mappings += 1;
+	}
+
+	amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {
+		if (num_mappings < args->num_entries) {
+			vm_buckets[num_mappings].start = mapping->start;
+			vm_buckets[num_mappings].last = mapping->last;
+			vm_buckets[num_mappings].offset = mapping->offset;
+			vm_buckets[num_mappings].flags = mapping->flags;
+		}
+		num_mappings += 1;
+	}
+
+	if (num_mappings > 0 && num_mappings <= args->num_entries)
+		ret = copy_to_user(u64_to_user_ptr(args->value), vm_buckets, num_mappings * sizeof(*vm_buckets));
+
+	args->num_entries = num_mappings;
+
+unlock_exec:
+	drm_exec_fini(&exec);
+	kvfree(vm_buckets);
+
+	return ret;
+}
+
 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *filp)
 {
@@ -1022,6 +1102,10 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
 
 		amdgpu_bo_unreserve(robj);
 		break;
+	case AMDGPU_GEM_OP_GET_MAPPING_INFO:
+		amdgpu_bo_unreserve(robj);
+		r = amdgpu_gem_list_mappings(gobj, filp->driver_priv, args);
+		break;
 	default:
 		amdgpu_bo_unreserve(robj);
 		r = -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index f9549f6b3d1f..5a63ae490b0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -668,4 +668,9 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
 				 struct amdgpu_vm *vm,
 				 struct dma_fence **fence);
 
+#define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \
+		list_for_each_entry(mapping, &bo_va->valids, list)
+#define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \
+		list_for_each_entry(mapping, &bo_va->invalids, list)
+
 #endif
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 59b423883e91..7072959103e6 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -802,6 +802,21 @@ union drm_amdgpu_wait_fences {
 
 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO	0
 #define AMDGPU_GEM_OP_SET_PLACEMENT		1
+#define AMDGPU_GEM_OP_GET_MAPPING_INFO		2
+
+struct drm_amdgpu_gem_vm_bucket {
+	/* Start of mapping (in number of pages) */
+	__u64 start;
+
+	/* End of mapping (in number of pages) */
+	__u64 last;
+
+	/* Mapping offset */
+	__u64 offset;
+
+	/* flags needed to recreate mapping */
+	__u64 flags;
+};
 
 /* Sets or returns a value associated with a buffer. */
 struct drm_amdgpu_gem_op {
@@ -811,6 +826,9 @@ struct drm_amdgpu_gem_op {
 	__u32	op;
 	/** Input or return value */
 	__u64	value;
+	/** For MAPPING_INFO op: number of mappings (in/out) */
+	__u32	num_entries;
+	__u32	padding;
 };
 
 #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT	(1 << 0)
-- 
2.34.1

[PATCH v12 3/3] drm/amdgpu: Allow kfd CRIU with no buffer objects

[David Francis]

The kfd CRIU checkpoint ioctl would return an error if trying
to checkpoint a process with no kfd buffer objects.

This is a normal case and should not be an error.

Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: David Francis <David.Francis@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 828a9ceef1e7..f7f34b710d3e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -2566,8 +2566,8 @@ static int criu_restore(struct file *filep,
 	pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
 		 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
 
-	if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
-	    !args->num_devices || !args->num_bos)
+	if ((args->num_bos > 0 && !args->bos) || !args->devices || !args->priv_data ||
+	    !args->priv_data_size || !args->num_devices)
 		return -EINVAL;
 
 	mutex_lock(&p->mutex);
-- 
2.34.1

Re: [PATCH v12 2/3] drm/amdgpu: Add mapping info option for GEM_OP ioctl

[Tvrtko Ursulin]

On 11/08/2025 16:05, David Francis wrote:
> Add new GEM_OP_IOCTL option GET_MAPPING_INFO, which
> returns a list of mappings associated with a given bo, along with
> their positions and offsets.
> 
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++++++++++++++++++++-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  5 ++
>   include/uapi/drm/amdgpu_drm.h           | 18 ++++++
>   3 files changed, 108 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 3873d2c19b4b..1632460623b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -885,7 +885,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>   				goto error;
>   		}
>   
> -		r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
> +		r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0);

Why is this new hunk related? Is it becase I asked what are the two 
reserved slots in amdgpu_gem_list_mappings() for? But that one remained 
so it is all unclear to me.

>   		drm_exec_retry_on_contention(&exec);
>   		if (unlikely(r))
>   			goto error;
> @@ -956,6 +956,86 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>   	return r;
>   }
>   
> +/**
> + * amdgpu_gem_list_mappings - get information about a buffer's mappings
> + *
> + * @gobj: gem object
> + * @args: gem_op arguments
> + * @fpriv: drm file pointer
> + *
> + * num_entries is set as an input to the size of the user-allocated array of
> + * drm_amdgpu_gem_vm_bucket stored at args->value.
> + * num_entries is sent back as output as the number of mappings the bo has.
> + * If that number is larger than the size of the array, the ioctl must
> + * be retried.
> + *
> + * Returns:
> + * 0 for success, -errno for errors.
> + */
> +static int amdgpu_gem_list_mappings(struct drm_gem_object *gobj, struct amdgpu_fpriv *fpriv,
> +					  struct drm_amdgpu_gem_op *args)
> +{
> +	struct amdgpu_vm *avm = &fpriv->vm;
> +	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
> +	struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(avm, bo);
> +	struct drm_amdgpu_gem_vm_bucket *vm_buckets;
> +	struct amdgpu_bo_va_mapping *mapping;
> +	struct drm_exec exec;
> +	int num_mappings = 0;
> +	int ret;
> +
> +	vm_buckets = kvcalloc(args->num_entries, sizeof(*vm_buckets), GFP_KERNEL);
> +	if (!vm_buckets)
> +		return -ENOMEM;
> +
> +	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
> +			  DRM_EXEC_IGNORE_DUPLICATES, 0);
> +	drm_exec_until_all_locked(&exec) {
> +		if (gobj) {
> +			ret = drm_exec_lock_obj(&exec, gobj);
> +			drm_exec_retry_on_contention(&exec);
> +			if (ret)
> +				goto unlock_exec;
> +		}
> +
> +		ret = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
> +		drm_exec_retry_on_contention(&exec);
> +		if (ret)
> +			goto unlock_exec;
> +	}
> +
> +	amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {
> +		if (num_mappings < args->num_entries) {
> +			vm_buckets[num_mappings].start = mapping->start;
> +			vm_buckets[num_mappings].last = mapping->last;
> +			vm_buckets[num_mappings].offset = mapping->offset;
> +			vm_buckets[num_mappings].flags = mapping->flags;
> +		}
> +		num_mappings += 1;
> +	}
> +
> +	amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {
> +		if (num_mappings < args->num_entries) {
> +			vm_buckets[num_mappings].start = mapping->start;
> +			vm_buckets[num_mappings].last = mapping->last;
> +			vm_buckets[num_mappings].offset = mapping->offset;
> +			vm_buckets[num_mappings].flags = mapping->flags;
> +		}
> +		num_mappings += 1;
> +	}
> +
> +	if (num_mappings > 0 && num_mappings <= args->num_entries)
> +		ret = copy_to_user(u64_to_user_ptr(args->value), vm_buckets, num_mappings * sizeof(*vm_buckets));
> +
> +	args->num_entries = num_mappings;
> +
> +unlock_exec:
> +	drm_exec_fini(&exec);
> +	kvfree(vm_buckets);
> +
> +	return ret;
> +}
> +
>   int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>   			struct drm_file *filp)
>   {
> @@ -1022,6 +1102,10 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>   
>   		amdgpu_bo_unreserve(robj);
>   		break;
> +	case AMDGPU_GEM_OP_GET_MAPPING_INFO:
> +		amdgpu_bo_unreserve(robj);
> +		r = amdgpu_gem_list_mappings(gobj, filp->driver_priv, args);
> +		break;
>   	default:
>   		amdgpu_bo_unreserve(robj);
>   		r = -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index f9549f6b3d1f..5a63ae490b0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -668,4 +668,9 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
>   				 struct amdgpu_vm *vm,
>   				 struct dma_fence **fence);
>   
> +#define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \
> +		list_for_each_entry(mapping, &bo_va->valids, list)
> +#define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \
> +		list_for_each_entry(mapping, &bo_va->invalids, list)
> +
>   #endif
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 59b423883e91..7072959103e6 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -802,6 +802,21 @@ union drm_amdgpu_wait_fences {
>   
>   #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO	0
>   #define AMDGPU_GEM_OP_SET_PLACEMENT		1
> +#define AMDGPU_GEM_OP_GET_MAPPING_INFO		2
> +
> +struct drm_amdgpu_gem_vm_bucket {
> +	/* Start of mapping (in number of pages) */
> +	__u64 start;
> +
> +	/* End of mapping (in number of pages) */
> +	__u64 last;
> +
> +	/* Mapping offset */
> +	__u64 offset;
> +
> +	/* flags needed to recreate mapping */
> +	__u64 flags;
> +};
>   
>   /* Sets or returns a value associated with a buffer. */
>   struct drm_amdgpu_gem_op {
> @@ -811,6 +826,9 @@ struct drm_amdgpu_gem_op {
>   	__u32	op;
>   	/** Input or return value */
>   	__u64	value;
> +	/** For MAPPING_INFO op: number of mappings (in/out) */
> +	__u32	num_entries;
> +	__u32	padding;

I suppose uapi kerneldoc should explain the value field is also used for 
AMDGPU_GEM_OP_GET_MAPPING_INFO and for what.

Alternatively union could be used to self document it but not sure if 
that is acceptable for amdgpu_drm.h? Like:

struct drm_amdgpu_gem_op {
	/** GEM object handle */
	__u32	handle;
	/** AMDGPU_GEM_OP_* */
	__u32	op;
	union {
		/** Input or return value */
		__u64	value;

		/** AMDGPU_GEM_OP_GET_MAPPING_INFO */
		struct {
			__u64 entries; /** Pointer to struct drm_amdgpu_gem_vm_bucket array 
(out) */
			__u64 num_entries; /** Number of mappings (in/out) */
		};
	};
};

Just a thought.

Regards,

Tvrtko

>   };
>   
>   #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT	(1 << 0)

Re: [PATCH v12 2/3] drm/amdgpu: Add mapping info option for GEM_OP ioctl

[Christian König]

On 12.08.25 11:20, Tvrtko Ursulin wrote:
> 
> On 11/08/2025 16:05, David Francis wrote:
>> Add new GEM_OP_IOCTL option GET_MAPPING_INFO, which
>> returns a list of mappings associated with a given bo, along with
>> their positions and offsets.
>>
>> Signed-off-by: David Francis <David.Francis@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++++++++++++++++++++-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  5 ++
>>   include/uapi/drm/amdgpu_drm.h           | 18 ++++++
>>   3 files changed, 108 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index 3873d2c19b4b..1632460623b2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -885,7 +885,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>                   goto error;
>>           }
>>   -        r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
>> +        r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0);
> 
> Why is this new hunk related? Is it becase I asked what are the two reserved slots in amdgpu_gem_list_mappings() for? But that one remained so it is all unclear to me.

Yeah that looks like a bug to me. The change was most likely applied to the wrong code.



> 
>>           drm_exec_retry_on_contention(&exec);
>>           if (unlikely(r))
>>               goto error;
>> @@ -956,6 +956,86 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>       return r;
>>   }
>>   +/**
>> + * amdgpu_gem_list_mappings - get information about a buffer's mappings
>> + *
>> + * @gobj: gem object
>> + * @args: gem_op arguments
>> + * @fpriv: drm file pointer
>> + *
>> + * num_entries is set as an input to the size of the user-allocated array of
>> + * drm_amdgpu_gem_vm_bucket stored at args->value.
>> + * num_entries is sent back as output as the number of mappings the bo has.
>> + * If that number is larger than the size of the array, the ioctl must
>> + * be retried.
>> + *
>> + * Returns:
>> + * 0 for success, -errno for errors.
>> + */
>> +static int amdgpu_gem_list_mappings(struct drm_gem_object *gobj, struct amdgpu_fpriv *fpriv,
>> +                      struct drm_amdgpu_gem_op *args)
>> +{
>> +    struct amdgpu_vm *avm = &fpriv->vm;
>> +    struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
>> +    struct amdgpu_bo_va *bo_va = amdgpu_vm_bo_find(avm, bo);
>> +    struct drm_amdgpu_gem_vm_bucket *vm_buckets;
>> +    struct amdgpu_bo_va_mapping *mapping;
>> +    struct drm_exec exec;
>> +    int num_mappings = 0;
>> +    int ret;
>> +
>> +    vm_buckets = kvcalloc(args->num_entries, sizeof(*vm_buckets), GFP_KERNEL);
>> +    if (!vm_buckets)
>> +        return -ENOMEM;
>> +
>> +    drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
>> +              DRM_EXEC_IGNORE_DUPLICATES, 0);
>> +    drm_exec_until_all_locked(&exec) {
>> +        if (gobj) {
>> +            ret = drm_exec_lock_obj(&exec, gobj);
>> +            drm_exec_retry_on_contention(&exec);
>> +            if (ret)
>> +                goto unlock_exec;
>> +        }
>> +
>> +        ret = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 2);
>> +        drm_exec_retry_on_contention(&exec);
>> +        if (ret)
>> +            goto unlock_exec;
>> +    }
>> +
>> +    amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) {
>> +        if (num_mappings < args->num_entries) {
>> +            vm_buckets[num_mappings].start = mapping->start;
>> +            vm_buckets[num_mappings].last = mapping->last;
>> +            vm_buckets[num_mappings].offset = mapping->offset;
>> +            vm_buckets[num_mappings].flags = mapping->flags;
>> +        }
>> +        num_mappings += 1;
>> +    }
>> +
>> +    amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) {
>> +        if (num_mappings < args->num_entries) {
>> +            vm_buckets[num_mappings].start = mapping->start;
>> +            vm_buckets[num_mappings].last = mapping->last;
>> +            vm_buckets[num_mappings].offset = mapping->offset;
>> +            vm_buckets[num_mappings].flags = mapping->flags;
>> +        }
>> +        num_mappings += 1;
>> +    }
>> +
>> +    if (num_mappings > 0 && num_mappings <= args->num_entries)
>> +        ret = copy_to_user(u64_to_user_ptr(args->value), vm_buckets, num_mappings * sizeof(*vm_buckets));
>> +
>> +    args->num_entries = num_mappings;
>> +
>> +unlock_exec:
>> +    drm_exec_fini(&exec);
>> +    kvfree(vm_buckets);
>> +
>> +    return ret;
>> +}
>> +
>>   int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>               struct drm_file *filp)
>>   {
>> @@ -1022,6 +1102,10 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>             amdgpu_bo_unreserve(robj);
>>           break;
>> +    case AMDGPU_GEM_OP_GET_MAPPING_INFO:
>> +        amdgpu_bo_unreserve(robj);
>> +        r = amdgpu_gem_list_mappings(gobj, filp->driver_priv, args);
>> +        break;
>>       default:
>>           amdgpu_bo_unreserve(robj);
>>           r = -EINVAL;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index f9549f6b3d1f..5a63ae490b0e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -668,4 +668,9 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev,
>>                    struct amdgpu_vm *vm,
>>                    struct dma_fence **fence);
>>   +#define amdgpu_vm_bo_va_for_each_valid_mapping(bo_va, mapping) \
>> +        list_for_each_entry(mapping, &bo_va->valids, list)
>> +#define amdgpu_vm_bo_va_for_each_invalid_mapping(bo_va, mapping) \
>> +        list_for_each_entry(mapping, &bo_va->invalids, list)
>> +
>>   #endif
>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
>> index 59b423883e91..7072959103e6 100644
>> --- a/include/uapi/drm/amdgpu_drm.h
>> +++ b/include/uapi/drm/amdgpu_drm.h
>> @@ -802,6 +802,21 @@ union drm_amdgpu_wait_fences {
>>     #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO    0
>>   #define AMDGPU_GEM_OP_SET_PLACEMENT        1
>> +#define AMDGPU_GEM_OP_GET_MAPPING_INFO        2
>> +
>> +struct drm_amdgpu_gem_vm_bucket {
>> +    /* Start of mapping (in number of pages) */
>> +    __u64 start;
>> +
>> +    /* End of mapping (in number of pages) */
>> +    __u64 last;
>> +
>> +    /* Mapping offset */
>> +    __u64 offset;
>> +
>> +    /* flags needed to recreate mapping */
>> +    __u64 flags;
>> +};
>>     /* Sets or returns a value associated with a buffer. */
>>   struct drm_amdgpu_gem_op {
>> @@ -811,6 +826,9 @@ struct drm_amdgpu_gem_op {
>>       __u32    op;
>>       /** Input or return value */
>>       __u64    value;
>> +    /** For MAPPING_INFO op: number of mappings (in/out) */
>> +    __u32    num_entries;
>> +    __u32    padding;
> 
> I suppose uapi kerneldoc should explain the value field is also used for AMDGPU_GEM_OP_GET_MAPPING_INFO and for what.
> 
> Alternatively union could be used to self document it but not sure if that is acceptable for amdgpu_drm.h? Like:
> 
> struct drm_amdgpu_gem_op {
>     /** GEM object handle */
>     __u32    handle;
>     /** AMDGPU_GEM_OP_* */
>     __u32    op;
>     union {
>         /** Input or return value */
>         __u64    value;
> 
>         /** AMDGPU_GEM_OP_GET_MAPPING_INFO */
>         struct {
>             __u64 entries; /** Pointer to struct drm_amdgpu_gem_vm_bucket array (out) */
>             __u64 num_entries; /** Number of mappings (in/out) */
>         };
>     };
> };
> 
> Just a thought.

Na, that looks quite ugly I think.

Extending the structure at the end is perfectly supported, but with the union you need to be really careful not to mess things up.

Regards,
Christian.

> 
> Regards,
> 
> Tvrtko
> 
>>   };
>>     #define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT    (1 << 0)
> 

Re: [PATCH v12 1/3] drm/amdgpu: Add ioctl to get all gem handles for a process

[Tvrtko Ursulin]

On 11/08/2025 16:05, David Francis wrote:
> Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES.
> 
> This ioctl returns a list of bos with their handles, sizes,
> and flags and domains.
> 
> This ioctl is meant to be used during CRIU checkpoint and
> provide information needed to reconstruct the bos
> in CRIU restore.
> 
> Signed-off-by: David Francis <David.Francis@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 83 +++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h |  2 +
>   include/uapi/drm/amdgpu_drm.h           | 31 +++++++++
>   4 files changed, 117 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4ff3a2eaaf55..f19795dddf9d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -3031,6 +3031,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>   	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
> +	DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>   };
>   
>   static const struct drm_driver amdgpu_kms_driver = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index e3f65977eeee..3873d2c19b4b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -1032,6 +1032,89 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>   	return r;
>   }
>   
> +/**
> + * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
> + *
> + * @dev: drm device pointer
> + * @data: drm_amdgpu_gem_list_handles
> + * @filp: drm file pointer
> + *
> + * num_bos is set as an input to the size of the bo_buckets array.
> + * num_bos is sent back as output as the number of bos in the process.
> + * If that number is larger than the size of the array, the ioctl must
> + * be retried.
> + *
> + * Returns:
> + * 0 for success, -errno for errors.
> + */
> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
> +			      struct drm_file *filp)
> +{
> +	struct drm_amdgpu_gem_list_handles *args = data;
> +	struct drm_amdgpu_gem_list_handles_entry *bo_entries;
> +	struct drm_gem_object *gobj;
> +	int id, ret = 0;
> +	int bo_index = 0;
> +	int num_bos = 0;
> +
> +	spin_lock(&filp->table_lock);
> +	idr_for_each_entry(&filp->object_idr, gobj, id)
> +		num_bos += 1;
> +	spin_unlock(&filp->table_lock);
> +
> +	if (args->num_entries < num_bos) {
> +		args->num_entries = num_bos;
> +		return 0;
> +	}
> +
> +	if (num_bos == 0) {
> +		args->num_entries = 0;
> +		return 0;
> +	}
> +
> +	bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
> +	if (!bo_entries)
> +		return -ENOMEM;
> +
> +	spin_lock(&filp->table_lock);
> +	idr_for_each_entry(&filp->object_idr, gobj, id) {
> +		struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
> +		struct drm_amdgpu_gem_list_handles_entry *bo_entry;
> +
> +		if (bo_index >= num_bos) {
> +			ret = -EAGAIN;
> +			break;
> +		}
> +
> +		bo_entry = &bo_entries[bo_index];
> +
> +		bo_entry->size = amdgpu_bo_size(bo);
> +		bo_entry->alloc_flags = bo->flags & (~AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE);
> +		/* WIPE_ON_RELEASE is set automatically in the driver; it is not permitted in
> +		 * BO creation. In the interest of giving the user exactly the flags they need
> +		 * to recreate the BO, clear it.
> +		 */

Ha, curious. What is the reason flags userspace cannot use are specified 
in the uapi header?

> +		bo_entry->preferred_domains = bo->preferred_domains;
> +		bo_entry->gem_handle = id;
> +
> +		if (bo->tbo.base.import_attach)
> +			bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;

I had a question regarding this part in v11. Any comment on that?

Anyway, thanks for implementing the other changes I suggested, this one 
LGTM now.

Regards,

Tvrtko

> +
> +		bo_index += 1;
> +	}
> +	spin_unlock(&filp->table_lock);
> +
> +	args->num_entries = bo_index;
> +
> +	if (!ret)
> +		ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries));
> +
> +	kvfree(bo_entries);
> +
> +	return ret;
> +}
> +
> +
>   static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
>   				  int width,
>   				  int cpp,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
> index b51e8f95ee86..7cdb6237bb92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
> @@ -67,6 +67,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>   			  struct drm_file *filp);
>   int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>   			struct drm_file *filp);
> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
> +			      struct drm_file *filp);
>   
>   int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
>   				struct drm_file *filp);
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index bdedbaccf776..59b423883e91 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -57,6 +57,7 @@ extern "C" {
>   #define DRM_AMDGPU_USERQ		0x16
>   #define DRM_AMDGPU_USERQ_SIGNAL		0x17
>   #define DRM_AMDGPU_USERQ_WAIT		0x18
> +#define DRM_AMDGPU_GEM_LIST_HANDLES	0x19
>   
>   #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>   #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
> @@ -77,6 +78,7 @@ extern "C" {
>   #define DRM_IOCTL_AMDGPU_USERQ		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>   #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
>   #define DRM_IOCTL_AMDGPU_USERQ_WAIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
> +#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>   
>   /**
>    * DOC: memory domains
> @@ -811,6 +813,35 @@ struct drm_amdgpu_gem_op {
>   	__u64	value;
>   };
>   
> +#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT	(1 << 0)
> +
> +struct drm_amdgpu_gem_list_handles {
> +	/* User pointer to array of drm_amdgpu_gem_bo_info_entry */
> +	__u64   entries;
> +
> +	/* IN: Size of entries buffer. OUT: Number of handles in process (if larger than size of buffer, must retry) */
> +	__u32   num_entries;
> +
> +	__u32 padding;
> +};
> +
> +struct drm_amdgpu_gem_list_handles_entry {
> +	/* gem handle of buffer object */
> +	__u32 gem_handle;
> +
> +	/* Currently just one flag: IS_IMPORT */
> +	__u32 flags;
> +
> +	/* Size of bo */
> +	__u64 size;
> +
> +	/* Preferred domains for GEM_CREATE */
> +	__u64 preferred_domains;
> +
> +	/* GEM_CREATE flags for re-creation of buffer */
> +	__u64 alloc_flags;
> +};
> +
>   #define AMDGPU_VA_OP_MAP			1
>   #define AMDGPU_VA_OP_UNMAP			2
>   #define AMDGPU_VA_OP_CLEAR			3

Re: [PATCH v12 1/3] drm/amdgpu: Add ioctl to get all gem handles for a process

[Christian König]

On 12.08.25 11:28, Tvrtko Ursulin wrote:
> 
> On 11/08/2025 16:05, David Francis wrote:
>> Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES.
>>
>> This ioctl returns a list of bos with their handles, sizes,
>> and flags and domains.
>>
>> This ioctl is meant to be used during CRIU checkpoint and
>> provide information needed to reconstruct the bos
>> in CRIU restore.
>>
>> Signed-off-by: David Francis <David.Francis@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 83 +++++++++++++++++++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h |  2 +
>>   include/uapi/drm/amdgpu_drm.h           | 31 +++++++++
>>   4 files changed, 117 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 4ff3a2eaaf55..f19795dddf9d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -3031,6 +3031,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>       DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>> +    DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>   };
>>     static const struct drm_driver amdgpu_kms_driver = {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index e3f65977eeee..3873d2c19b4b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -1032,6 +1032,89 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>       return r;
>>   }
>>   +/**
>> + * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
>> + *
>> + * @dev: drm device pointer
>> + * @data: drm_amdgpu_gem_list_handles
>> + * @filp: drm file pointer
>> + *
>> + * num_bos is set as an input to the size of the bo_buckets array.
>> + * num_bos is sent back as output as the number of bos in the process.
>> + * If that number is larger than the size of the array, the ioctl must
>> + * be retried.
>> + *
>> + * Returns:
>> + * 0 for success, -errno for errors.
>> + */
>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>> +                  struct drm_file *filp)
>> +{
>> +    struct drm_amdgpu_gem_list_handles *args = data;
>> +    struct drm_amdgpu_gem_list_handles_entry *bo_entries;
>> +    struct drm_gem_object *gobj;
>> +    int id, ret = 0;
>> +    int bo_index = 0;
>> +    int num_bos = 0;
>> +
>> +    spin_lock(&filp->table_lock);
>> +    idr_for_each_entry(&filp->object_idr, gobj, id)
>> +        num_bos += 1;
>> +    spin_unlock(&filp->table_lock);
>> +
>> +    if (args->num_entries < num_bos) {
>> +        args->num_entries = num_bos;
>> +        return 0;
>> +    }
>> +
>> +    if (num_bos == 0) {
>> +        args->num_entries = 0;
>> +        return 0;
>> +    }
>> +
>> +    bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
>> +    if (!bo_entries)
>> +        return -ENOMEM;
>> +
>> +    spin_lock(&filp->table_lock);
>> +    idr_for_each_entry(&filp->object_idr, gobj, id) {
>> +        struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
>> +        struct drm_amdgpu_gem_list_handles_entry *bo_entry;
>> +
>> +        if (bo_index >= num_bos) {
>> +            ret = -EAGAIN;
>> +            break;
>> +        }
>> +
>> +        bo_entry = &bo_entries[bo_index];
>> +
>> +        bo_entry->size = amdgpu_bo_size(bo);
>> +        bo_entry->alloc_flags = bo->flags & (~AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE);
>> +        /* WIPE_ON_RELEASE is set automatically in the driver; it is not permitted in
>> +         * BO creation. In the interest of giving the user exactly the flags they need
>> +         * to recreate the BO, clear it.
>> +         */
> 
> Ha, curious. What is the reason flags userspace cannot use are specified in the uapi header?

The comment isn't correct. AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE is perfectly allowed in the create IOCTL.

Regards,
Christian.

> 
>> +        bo_entry->preferred_domains = bo->preferred_domains;
>> +        bo_entry->gem_handle = id;
>> +
>> +        if (bo->tbo.base.import_attach)
>> +            bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
> 
> I had a question regarding this part in v11. Any comment on that?
> 
> Anyway, thanks for implementing the other changes I suggested, this one LGTM now.
> 
> Regards,
> 
> Tvrtko
> 
>> +
>> +        bo_index += 1;
>> +    }
>> +    spin_unlock(&filp->table_lock);
>> +
>> +    args->num_entries = bo_index;
>> +
>> +    if (!ret)
>> +        ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries));
>> +
>> +    kvfree(bo_entries);
>> +
>> +    return ret;
>> +}
>> +
>> +
>>   static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
>>                     int width,
>>                     int cpp,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>> index b51e8f95ee86..7cdb6237bb92 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>> @@ -67,6 +67,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>                 struct drm_file *filp);
>>   int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>               struct drm_file *filp);
>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>> +                  struct drm_file *filp);
>>     int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
>>                   struct drm_file *filp);
>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
>> index bdedbaccf776..59b423883e91 100644
>> --- a/include/uapi/drm/amdgpu_drm.h
>> +++ b/include/uapi/drm/amdgpu_drm.h
>> @@ -57,6 +57,7 @@ extern "C" {
>>   #define DRM_AMDGPU_USERQ        0x16
>>   #define DRM_AMDGPU_USERQ_SIGNAL        0x17
>>   #define DRM_AMDGPU_USERQ_WAIT        0x18
>> +#define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>     #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>   #define DRM_IOCTL_AMDGPU_GEM_MMAP    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>> @@ -77,6 +78,7 @@ extern "C" {
>>   #define DRM_IOCTL_AMDGPU_USERQ        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>>   #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
>>   #define DRM_IOCTL_AMDGPU_USERQ_WAIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>> +#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>>     /**
>>    * DOC: memory domains
>> @@ -811,6 +813,35 @@ struct drm_amdgpu_gem_op {
>>       __u64    value;
>>   };
>>   +#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT    (1 << 0)
>> +
>> +struct drm_amdgpu_gem_list_handles {
>> +    /* User pointer to array of drm_amdgpu_gem_bo_info_entry */
>> +    __u64   entries;
>> +
>> +    /* IN: Size of entries buffer. OUT: Number of handles in process (if larger than size of buffer, must retry) */
>> +    __u32   num_entries;
>> +
>> +    __u32 padding;
>> +};
>> +
>> +struct drm_amdgpu_gem_list_handles_entry {
>> +    /* gem handle of buffer object */
>> +    __u32 gem_handle;
>> +
>> +    /* Currently just one flag: IS_IMPORT */
>> +    __u32 flags;
>> +
>> +    /* Size of bo */
>> +    __u64 size;
>> +
>> +    /* Preferred domains for GEM_CREATE */
>> +    __u64 preferred_domains;
>> +
>> +    /* GEM_CREATE flags for re-creation of buffer */
>> +    __u64 alloc_flags;
>> +};
>> +
>>   #define AMDGPU_VA_OP_MAP            1
>>   #define AMDGPU_VA_OP_UNMAP            2
>>   #define AMDGPU_VA_OP_CLEAR            3
> 

Re: [PATCH v12 1/3] drm/amdgpu: Add ioctl to get all gem handles for a process

[Tvrtko Ursulin]

On 12/08/2025 10:36, Christian König wrote:
> On 12.08.25 11:28, Tvrtko Ursulin wrote:
>>
>> On 11/08/2025 16:05, David Francis wrote:
>>> Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES.
>>>
>>> This ioctl returns a list of bos with their handles, sizes,
>>> and flags and domains.
>>>
>>> This ioctl is meant to be used during CRIU checkpoint and
>>> provide information needed to reconstruct the bos
>>> in CRIU restore.
>>>
>>> Signed-off-by: David Francis <David.Francis@amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  1 +
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 83 +++++++++++++++++++++++++
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h |  2 +
>>>    include/uapi/drm/amdgpu_drm.h           | 31 +++++++++
>>>    4 files changed, 117 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> index 4ff3a2eaaf55..f19795dddf9d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> @@ -3031,6 +3031,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>> +    DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>    };
>>>      static const struct drm_driver amdgpu_kms_driver = {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> index e3f65977eeee..3873d2c19b4b 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>> @@ -1032,6 +1032,89 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>>        return r;
>>>    }
>>>    +/**
>>> + * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
>>> + *
>>> + * @dev: drm device pointer
>>> + * @data: drm_amdgpu_gem_list_handles
>>> + * @filp: drm file pointer
>>> + *
>>> + * num_bos is set as an input to the size of the bo_buckets array.
>>> + * num_bos is sent back as output as the number of bos in the process.
>>> + * If that number is larger than the size of the array, the ioctl must
>>> + * be retried.
>>> + *
>>> + * Returns:
>>> + * 0 for success, -errno for errors.
>>> + */
>>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>>> +                  struct drm_file *filp)
>>> +{
>>> +    struct drm_amdgpu_gem_list_handles *args = data;
>>> +    struct drm_amdgpu_gem_list_handles_entry *bo_entries;
>>> +    struct drm_gem_object *gobj;
>>> +    int id, ret = 0;
>>> +    int bo_index = 0;
>>> +    int num_bos = 0;
>>> +
>>> +    spin_lock(&filp->table_lock);
>>> +    idr_for_each_entry(&filp->object_idr, gobj, id)
>>> +        num_bos += 1;
>>> +    spin_unlock(&filp->table_lock);
>>> +
>>> +    if (args->num_entries < num_bos) {
>>> +        args->num_entries = num_bos;
>>> +        return 0;
>>> +    }
>>> +
>>> +    if (num_bos == 0) {
>>> +        args->num_entries = 0;
>>> +        return 0;
>>> +    }
>>> +
>>> +    bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
>>> +    if (!bo_entries)
>>> +        return -ENOMEM;
>>> +
>>> +    spin_lock(&filp->table_lock);
>>> +    idr_for_each_entry(&filp->object_idr, gobj, id) {
>>> +        struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
>>> +        struct drm_amdgpu_gem_list_handles_entry *bo_entry;
>>> +
>>> +        if (bo_index >= num_bos) {
>>> +            ret = -EAGAIN;
>>> +            break;
>>> +        }
>>> +
>>> +        bo_entry = &bo_entries[bo_index];
>>> +
>>> +        bo_entry->size = amdgpu_bo_size(bo);
>>> +        bo_entry->alloc_flags = bo->flags & (~AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE);
>>> +        /* WIPE_ON_RELEASE is set automatically in the driver; it is not permitted in
>>> +         * BO creation. In the interest of giving the user exactly the flags they need
>>> +         * to recreate the BO, clear it.
>>> +         */
>>
>> Ha, curious. What is the reason flags userspace cannot use are specified in the uapi header?
> 
> The comment isn't correct. AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE is perfectly allowed in the create IOCTL.

I looked after reading the comment and it seemed true:

amdgpu_gem_create_ioctl():
...
	uint64_t flags = args->in.domain_flags;
...
	/* reject invalid gem flags */
	if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
		      AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
		      AMDGPU_GEM_CREATE_CPU_GTT_USWC |
		      AMDGPU_GEM_CREATE_VRAM_CLEARED |
		      AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
		      AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
		      AMDGPU_GEM_CREATE_ENCRYPTED |
		      AMDGPU_GEM_CREATE_GFX12_DCC |
		      AMDGPU_GEM_CREATE_DISCARDABLE))
		return -EINVAL;

Actually, thinking about it more, maybe more flags should be cleared in 
amdgpu_gem_list_handles_ioctl()? Perhaps the above mask should be 
defined at a common place, or even internal only flags removed from the 
uapi header. Or uapi vs internal flags split or something.

Regards,

Tvrtko

>>
>>> +        bo_entry->preferred_domains = bo->preferred_domains;
>>> +        bo_entry->gem_handle = id;
>>> +
>>> +        if (bo->tbo.base.import_attach)
>>> +            bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
>>
>> I had a question regarding this part in v11. Any comment on that?
>>
>> Anyway, thanks for implementing the other changes I suggested, this one LGTM now.
>>
>> Regards,
>>
>> Tvrtko
>>
>>> +
>>> +        bo_index += 1;
>>> +    }
>>> +    spin_unlock(&filp->table_lock);
>>> +
>>> +    args->num_entries = bo_index;
>>> +
>>> +    if (!ret)
>>> +        ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries));
>>> +
>>> +    kvfree(bo_entries);
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +
>>>    static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
>>>                      int width,
>>>                      int cpp,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>> index b51e8f95ee86..7cdb6237bb92 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>> @@ -67,6 +67,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>>                  struct drm_file *filp);
>>>    int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>>                struct drm_file *filp);
>>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>>> +                  struct drm_file *filp);
>>>      int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
>>>                    struct drm_file *filp);
>>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
>>> index bdedbaccf776..59b423883e91 100644
>>> --- a/include/uapi/drm/amdgpu_drm.h
>>> +++ b/include/uapi/drm/amdgpu_drm.h
>>> @@ -57,6 +57,7 @@ extern "C" {
>>>    #define DRM_AMDGPU_USERQ        0x16
>>>    #define DRM_AMDGPU_USERQ_SIGNAL        0x17
>>>    #define DRM_AMDGPU_USERQ_WAIT        0x18
>>> +#define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>>      #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>>    #define DRM_IOCTL_AMDGPU_GEM_MMAP    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>>> @@ -77,6 +78,7 @@ extern "C" {
>>>    #define DRM_IOCTL_AMDGPU_USERQ        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>>>    #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
>>>    #define DRM_IOCTL_AMDGPU_USERQ_WAIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>>> +#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>>>      /**
>>>     * DOC: memory domains
>>> @@ -811,6 +813,35 @@ struct drm_amdgpu_gem_op {
>>>        __u64    value;
>>>    };
>>>    +#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT    (1 << 0)
>>> +
>>> +struct drm_amdgpu_gem_list_handles {
>>> +    /* User pointer to array of drm_amdgpu_gem_bo_info_entry */
>>> +    __u64   entries;
>>> +
>>> +    /* IN: Size of entries buffer. OUT: Number of handles in process (if larger than size of buffer, must retry) */
>>> +    __u32   num_entries;
>>> +
>>> +    __u32 padding;
>>> +};
>>> +
>>> +struct drm_amdgpu_gem_list_handles_entry {
>>> +    /* gem handle of buffer object */
>>> +    __u32 gem_handle;
>>> +
>>> +    /* Currently just one flag: IS_IMPORT */
>>> +    __u32 flags;
>>> +
>>> +    /* Size of bo */
>>> +    __u64 size;
>>> +
>>> +    /* Preferred domains for GEM_CREATE */
>>> +    __u64 preferred_domains;
>>> +
>>> +    /* GEM_CREATE flags for re-creation of buffer */
>>> +    __u64 alloc_flags;
>>> +};
>>> +
>>>    #define AMDGPU_VA_OP_MAP            1
>>>    #define AMDGPU_VA_OP_UNMAP            2
>>>    #define AMDGPU_VA_OP_CLEAR            3
>>
> 

Re: [PATCH v12 1/3] drm/amdgpu: Add ioctl to get all gem handles for a process

[Christian König]

On 12.08.25 11:56, Tvrtko Ursulin wrote:
> 
> On 12/08/2025 10:36, Christian König wrote:
>> On 12.08.25 11:28, Tvrtko Ursulin wrote:
>>>
>>> On 11/08/2025 16:05, David Francis wrote:
>>>> Add new ioctl DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES.
>>>>
>>>> This ioctl returns a list of bos with their handles, sizes,
>>>> and flags and domains.
>>>>
>>>> This ioctl is meant to be used during CRIU checkpoint and
>>>> provide information needed to reconstruct the bos
>>>> in CRIU restore.
>>>>
>>>> Signed-off-by: David Francis <David.Francis@amd.com>
>>>> ---
>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  1 +
>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 83 +++++++++++++++++++++++++
>>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h |  2 +
>>>>    include/uapi/drm/amdgpu_drm.h           | 31 +++++++++
>>>>    4 files changed, 117 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> index 4ff3a2eaaf55..f19795dddf9d 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>>> @@ -3031,6 +3031,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
>>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ, amdgpu_userq_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>>        DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>> +    DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>>>>    };
>>>>      static const struct drm_driver amdgpu_kms_driver = {
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>>> index e3f65977eeee..3873d2c19b4b 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>>>> @@ -1032,6 +1032,89 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>>>        return r;
>>>>    }
>>>>    +/**
>>>> + * drm_amdgpu_gem_list_handles_ioctl - get information about a process' buffer objects
>>>> + *
>>>> + * @dev: drm device pointer
>>>> + * @data: drm_amdgpu_gem_list_handles
>>>> + * @filp: drm file pointer
>>>> + *
>>>> + * num_bos is set as an input to the size of the bo_buckets array.
>>>> + * num_bos is sent back as output as the number of bos in the process.
>>>> + * If that number is larger than the size of the array, the ioctl must
>>>> + * be retried.
>>>> + *
>>>> + * Returns:
>>>> + * 0 for success, -errno for errors.
>>>> + */
>>>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>>>> +                  struct drm_file *filp)
>>>> +{
>>>> +    struct drm_amdgpu_gem_list_handles *args = data;
>>>> +    struct drm_amdgpu_gem_list_handles_entry *bo_entries;
>>>> +    struct drm_gem_object *gobj;
>>>> +    int id, ret = 0;
>>>> +    int bo_index = 0;
>>>> +    int num_bos = 0;
>>>> +
>>>> +    spin_lock(&filp->table_lock);
>>>> +    idr_for_each_entry(&filp->object_idr, gobj, id)
>>>> +        num_bos += 1;
>>>> +    spin_unlock(&filp->table_lock);
>>>> +
>>>> +    if (args->num_entries < num_bos) {
>>>> +        args->num_entries = num_bos;
>>>> +        return 0;
>>>> +    }
>>>> +
>>>> +    if (num_bos == 0) {
>>>> +        args->num_entries = 0;
>>>> +        return 0;
>>>> +    }
>>>> +
>>>> +    bo_entries = kvcalloc(num_bos, sizeof(*bo_entries), GFP_KERNEL);
>>>> +    if (!bo_entries)
>>>> +        return -ENOMEM;
>>>> +
>>>> +    spin_lock(&filp->table_lock);
>>>> +    idr_for_each_entry(&filp->object_idr, gobj, id) {
>>>> +        struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
>>>> +        struct drm_amdgpu_gem_list_handles_entry *bo_entry;
>>>> +
>>>> +        if (bo_index >= num_bos) {
>>>> +            ret = -EAGAIN;
>>>> +            break;
>>>> +        }
>>>> +
>>>> +        bo_entry = &bo_entries[bo_index];
>>>> +
>>>> +        bo_entry->size = amdgpu_bo_size(bo);
>>>> +        bo_entry->alloc_flags = bo->flags & (~AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE);
>>>> +        /* WIPE_ON_RELEASE is set automatically in the driver; it is not permitted in
>>>> +         * BO creation. In the interest of giving the user exactly the flags they need
>>>> +         * to recreate the BO, clear it.
>>>> +         */
>>>
>>> Ha, curious. What is the reason flags userspace cannot use are specified in the uapi header?
>>
>> The comment isn't correct. AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE is perfectly allowed in the create IOCTL.
> 
> I looked after reading the comment and it seemed true:

Oh, good point. Now I understand the issue. The GEM interface doesn't allowed for the flag on create!

> 
> amdgpu_gem_create_ioctl():
> ...
>     uint64_t flags = args->in.domain_flags;
> ...
>     /* reject invalid gem flags */
>     if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
>               AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
>               AMDGPU_GEM_CREATE_CPU_GTT_USWC |
>               AMDGPU_GEM_CREATE_VRAM_CLEARED |
>               AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
>               AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
>               AMDGPU_GEM_CREATE_ENCRYPTED |
>               AMDGPU_GEM_CREATE_GFX12_DCC |
>               AMDGPU_GEM_CREATE_DISCARDABLE))
>         return -EINVAL;
> 
> Actually, thinking about it more, maybe more flags should be cleared in amdgpu_gem_list_handles_ioctl()? Perhaps the above mask should be defined at a common place, or even internal only flags removed from the uapi header. Or uapi vs internal flags split or something.

Yeah, probably good idea. But it should most likely not be in an UAPI header.

The general background is that we have a bunch of flags only the kernel can set and are read only for userspace.

Regards,
Christian.

> 
> Regards,
> 
> Tvrtko
> 
>>>
>>>> +        bo_entry->preferred_domains = bo->preferred_domains;
>>>> +        bo_entry->gem_handle = id;
>>>> +
>>>> +        if (bo->tbo.base.import_attach)
>>>> +            bo_entry->flags |= AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT;
>>>
>>> I had a question regarding this part in v11. Any comment on that?
>>>
>>> Anyway, thanks for implementing the other changes I suggested, this one LGTM now.
>>>
>>> Regards,
>>>
>>> Tvrtko
>>>
>>>> +
>>>> +        bo_index += 1;
>>>> +    }
>>>> +    spin_unlock(&filp->table_lock);
>>>> +
>>>> +    args->num_entries = bo_index;
>>>> +
>>>> +    if (!ret)
>>>> +        ret = copy_to_user(u64_to_user_ptr(args->entries), bo_entries, num_bos * sizeof(*bo_entries));
>>>> +
>>>> +    kvfree(bo_entries);
>>>> +
>>>> +    return ret;
>>>> +}
>>>> +
>>>> +
>>>>    static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
>>>>                      int width,
>>>>                      int cpp,
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>>> index b51e8f95ee86..7cdb6237bb92 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>>>> @@ -67,6 +67,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>>>>                  struct drm_file *filp);
>>>>    int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
>>>>                struct drm_file *filp);
>>>> +int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
>>>> +                  struct drm_file *filp);
>>>>      int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
>>>>                    struct drm_file *filp);
>>>> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
>>>> index bdedbaccf776..59b423883e91 100644
>>>> --- a/include/uapi/drm/amdgpu_drm.h
>>>> +++ b/include/uapi/drm/amdgpu_drm.h
>>>> @@ -57,6 +57,7 @@ extern "C" {
>>>>    #define DRM_AMDGPU_USERQ        0x16
>>>>    #define DRM_AMDGPU_USERQ_SIGNAL        0x17
>>>>    #define DRM_AMDGPU_USERQ_WAIT        0x18
>>>> +#define DRM_AMDGPU_GEM_LIST_HANDLES    0x19
>>>>      #define DRM_IOCTL_AMDGPU_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
>>>>    #define DRM_IOCTL_AMDGPU_GEM_MMAP    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
>>>> @@ -77,6 +78,7 @@ extern "C" {
>>>>    #define DRM_IOCTL_AMDGPU_USERQ        DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
>>>>    #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
>>>>    #define DRM_IOCTL_AMDGPU_USERQ_WAIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
>>>> +#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
>>>>      /**
>>>>     * DOC: memory domains
>>>> @@ -811,6 +813,35 @@ struct drm_amdgpu_gem_op {
>>>>        __u64    value;
>>>>    };
>>>>    +#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT    (1 << 0)
>>>> +
>>>> +struct drm_amdgpu_gem_list_handles {
>>>> +    /* User pointer to array of drm_amdgpu_gem_bo_info_entry */
>>>> +    __u64   entries;
>>>> +
>>>> +    /* IN: Size of entries buffer. OUT: Number of handles in process (if larger than size of buffer, must retry) */
>>>> +    __u32   num_entries;
>>>> +
>>>> +    __u32 padding;
>>>> +};
>>>> +
>>>> +struct drm_amdgpu_gem_list_handles_entry {
>>>> +    /* gem handle of buffer object */
>>>> +    __u32 gem_handle;
>>>> +
>>>> +    /* Currently just one flag: IS_IMPORT */
>>>> +    __u32 flags;
>>>> +
>>>> +    /* Size of bo */
>>>> +    __u64 size;
>>>> +
>>>> +    /* Preferred domains for GEM_CREATE */
>>>> +    __u64 preferred_domains;
>>>> +
>>>> +    /* GEM_CREATE flags for re-creation of buffer */
>>>> +    __u64 alloc_flags;
>>>> +};
>>>> +
>>>>    #define AMDGPU_VA_OP_MAP            1
>>>>    #define AMDGPU_VA_OP_UNMAP            2
>>>>    #define AMDGPU_VA_OP_CLEAR            3
>>>
>>
>