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[2001:4c4e:24ca:a400:8825:f46d:d14d:d33]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b725f72a688sm52730166b.49.2025.11.04.07.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 07:16:15 -0800 (PST) Message-ID: <01cfdc57f76218039efb67226b9c08189f8a1b1e.camel@gmail.com> Subject: Re: [PATCH 09/16] drm/amdgpu/si,cik,vi: Verify IP block when querying video codecs (v2) From: Timur =?ISO-8859-1?Q?Krist=F3f?= To: Christian =?ISO-8859-1?Q?K=F6nig?= , amd-gfx@lists.freedesktop.org, Alex Deucher , Alexandre Demers , Rodrigo Siqueira , Leo Liu Date: Tue, 04 Nov 2025 16:16:12 +0100 In-Reply-To: <97a3a818-6526-4447-ab92-14a6eb9551a3@amd.com> References: <20251103222333.37817-1-timur.kristof@gmail.com> <20251103222333.37817-10-timur.kristof@gmail.com> <97a3a818-6526-4447-ab92-14a6eb9551a3@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tue, 2025-11-04 at 14:44 +0100, Christian K=C3=B6nig wrote: > On 11/3/25 23:23, Timur Krist=C3=B3f wrote: > > Some harvested chips may not have any IP blocks, > > or we may not have the firmware for the IP blocks. > > In these cases, the query should return that no video > > codec is supported. > >=20 > > v2: > > - When codecs is NULL, treat that as empty codec list. >=20 > I'm still not sure if returning an error instead wouldn't be better. >=20 > @Alex and Leo what do you guys think? >=20 > Regards, > Christian. Returning an error from this function would indicate to userspace that there was an error with querying the list of codecs. That is not what we want. We simply want to tell userspace that no codecs are supported. Thanks & best regards, Timur >=20 > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > > =C2=A0drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 +++++-- > > =C2=A0drivers/gpu/drm/amd/amdgpu/cik.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 | 6 ++++++ > > =C2=A0drivers/gpu/drm/amd/amdgpu/si.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 | 6 ++++++ > > =C2=A0drivers/gpu/drm/amd/amdgpu/vi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 | 6 ++++++ > > =C2=A04 files changed, 23 insertions(+), 2 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > index b3e6b3fcdf2c..71eceac58fb6 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > @@ -1263,8 +1263,9 @@ int amdgpu_info_ioctl(struct drm_device *dev, > > void *data, struct drm_file *filp) > > =C2=A0 -EFAULT : 0; > > =C2=A0 } > > =C2=A0 case AMDGPU_INFO_VIDEO_CAPS: { > > - const struct amdgpu_video_codecs *codecs; > > + const struct amdgpu_video_codecs *codecs =3D NULL; > > =C2=A0 struct drm_amdgpu_info_video_caps *caps; > > + u32 codec_count; > > =C2=A0 int r; > > =C2=A0 > > =C2=A0 if (!adev->asic_funcs->query_video_codecs) > > @@ -1291,7 +1292,9 @@ int amdgpu_info_ioctl(struct drm_device *dev, > > void *data, struct drm_file *filp) > > =C2=A0 if (!caps) > > =C2=A0 return -ENOMEM; > > =C2=A0 > > - for (i =3D 0; i < codecs->codec_count; i++) { > > + codec_count =3D codecs ? codecs->codec_count : 0; > > + > > + for (i =3D 0; i < codec_count; i++) { > > =C2=A0 int idx =3D codecs- > > >codec_array[i].codec_type; > > =C2=A0 > > =C2=A0 switch (idx) { > > diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c > > b/drivers/gpu/drm/amd/amdgpu/cik.c > > index 9cd63b4177bf..b755238c2c3d 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/cik.c > > +++ b/drivers/gpu/drm/amd/amdgpu/cik.c > > @@ -130,6 +130,12 @@ static const struct amdgpu_video_codecs > > cik_video_codecs_decode =3D > > =C2=A0static int cik_query_video_codecs(struct amdgpu_device *adev, boo= l > > encode, > > =C2=A0 =C2=A0 const struct amdgpu_video_codecs > > **codecs) > > =C2=A0{ > > + const enum amd_ip_block_type ip =3D > > + encode ? AMD_IP_BLOCK_TYPE_VCE : > > AMD_IP_BLOCK_TYPE_UVD; > > + > > + if (!amdgpu_device_ip_is_valid(adev, ip)) > > + return 0; > > + > > =C2=A0 switch (adev->asic_type) { > > =C2=A0 case CHIP_BONAIRE: > > =C2=A0 case CHIP_HAWAII: > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c > > b/drivers/gpu/drm/amd/amdgpu/si.c > > index e0f139de7991..9468c03bdb1b 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/si.c > > +++ b/drivers/gpu/drm/amd/amdgpu/si.c > > @@ -1003,6 +1003,12 @@ static const struct amdgpu_video_codecs > > hainan_video_codecs_decode =3D > > =C2=A0static int si_query_video_codecs(struct amdgpu_device *adev, bool > > encode, > > =C2=A0 const struct amdgpu_video_codecs > > **codecs) > > =C2=A0{ > > + const enum amd_ip_block_type ip =3D > > + encode ? AMD_IP_BLOCK_TYPE_VCE : > > AMD_IP_BLOCK_TYPE_UVD; > > + > > + if (!amdgpu_device_ip_is_valid(adev, ip)) > > + return 0; > > + > > =C2=A0 switch (adev->asic_type) { > > =C2=A0 case CHIP_VERDE: > > =C2=A0 case CHIP_TAHITI: > > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c > > b/drivers/gpu/drm/amd/amdgpu/vi.c > > index a611a7345125..f0e4193cf722 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/vi.c > > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c > > @@ -256,6 +256,12 @@ static const struct amdgpu_video_codecs > > cz_video_codecs_decode =3D > > =C2=A0static int vi_query_video_codecs(struct amdgpu_device *adev, bool > > encode, > > =C2=A0 const struct amdgpu_video_codecs > > **codecs) > > =C2=A0{ > > + const enum amd_ip_block_type ip =3D > > + encode ? AMD_IP_BLOCK_TYPE_VCE : > > AMD_IP_BLOCK_TYPE_UVD; > > + > > + if (!amdgpu_device_ip_is_valid(adev, ip)) > > + return 0; > > + > > =C2=A0 switch (adev->asic_type) { > > =C2=A0 case CHIP_TOPAZ: > > =C2=A0 if (encode)