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[94.27.152.162]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4dc24cfsm52420203f8f.16.2026.04.23.05.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Apr 2026 05:18:16 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com, John Olender , Christian =?UTF-8?B?S8O2bmln?= Subject: Re: [PATCH 01/11] drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti Date: Thu, 23 Apr 2026 14:18:15 +0200 Message-ID: <10056594.eNJFYEL58v@timur-hyperion> In-Reply-To: References: <20260423011614.309180-1-timur.kristof@gmail.com> <20260423011614.309180-2-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thursday, April 23, 2026 1:04:53=E2=80=AFPM Central European Summer Time= Christian=20 K=C3=B6nig wrote: > On 4/23/26 03:16, Timur Krist=C3=B3f wrote: > > The TLB is organized in groups of 8 entries, each one is 4K. > > On Tahiti, the HW requires these GART entries to be 32K-aligned. > >=20 > > This fixes a VCE 1 firmware validation failure that can happen > > after suspend/resume since we use amdgpu_gtt_mgr for VCE 1. > >=20 > > Fixes: 698fa62f56aa ("drm/amdgpu: Add helper to alloc GART entries") > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index > > 9b0bcf6aca445..673e9e08c66a0 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > @@ -198,12 +198,19 @@ int amdgpu_gtt_mgr_alloc_entries(struct > > amdgpu_gtt_mgr *mgr,>=20 > > u64 num_pages, > > enum drm_mm_insert_mode mode) > > =20 > > { > >=20 > > + u32 alignment =3D 0; > >=20 > > struct amdgpu_device *adev =3D container_of(mgr, typeof(*adev), > > mman.gtt_mgr); int r; >=20 > Only a nit, but reverse xmas tree order please for variable declarations. I haven't found this in the Linux coding style guide, can you elaborate wha= t=20 you are referring to exactly? >=20 > > + /* Align to TLB size on Tahiti */ >=20 > Oh that needs improvement. >=20 > Maybe something like /* Align to TLB L2 cache entry size to work around V > bit HW bug */ >=20 > Mostly nobody will know what that "V bit HW bug" is, but at least AMD peo= ple > can search for that in the HW docs. Sounds good, will add those details to the comments (and commit message) in the next version of the series. >=20 > With that fixed Reviewed-by: Christian K=C3=B6nig . >=20 > Thanks, > Christian. Thanks! >=20 > > + if (adev->asic_type =3D=3D CHIP_TAHITI) { > > + alignment =3D 32 * 1024 / AMDGPU_GPU_PAGE_SIZE; > > + num_pages =3D ALIGN(num_pages, alignment); > > + } > > + > >=20 > > spin_lock(&mgr->lock); > > r =3D drm_mm_insert_node_in_range(&mgr->mm, mm_node, num_pages, > >=20 > > - 0,=20 GART_ENTRY_WITHOUT_BO_COLOR, 0, > > + alignment,=20 GART_ENTRY_WITHOUT_BO_COLOR, 0, > >=20 > > adev->gmc.gart_size >>=20 PAGE_SHIFT, > > mode); > > =09 > > spin_unlock(&mgr->lock);