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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36075104c66sm1257195f8f.111.2024.06.13.03.19.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Jun 2024 03:19:37 -0700 (PDT) Message-ID: <114537d3-364f-46f4-8eb8-81785e461f92@gmail.com> Date: Thu, 13 Jun 2024 12:19:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] drm/amdgpu: wait for gpu to complete reset To: YiPeng Chai , amd-gfx@lists.freedesktop.org Cc: Hawking.Zhang@amd.com, Tao.Zhou1@amd.com, Candice.Li@amd.com, KevinYang.Wang@amd.com, Stanley.Yang@amd.com References: <20240613022504.81787-1-YiPeng.Chai@amd.com> <20240613022504.81787-4-YiPeng.Chai@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240613022504.81787-4-YiPeng.Chai@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 13.06.24 um 04:25 schrieb YiPeng Chai: > Add completion to wait for gpu to complete reset. > > Signed-off-by: YiPeng Chai > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 12 ++++++++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > index 7dfb2e548d70..341c9bd0d1a4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c > @@ -124,6 +124,8 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) > > #define AMDGPU_RAS_RETIRE_PAGE_INTERVAL 100 //ms > > +#define MAX_GPU_RESET_COMPLETION_TIME 120000 //ms > + > #define RAS_POISON_FIFO_MSG_PENDING_THRESHOLD (AMDGPU_RAS_POISON_FIFO_SIZE/4) > > enum amdgpu_ras_retire_page_reservation { > @@ -2526,6 +2528,8 @@ static void amdgpu_ras_do_recovery(struct work_struct *work) > atomic_set(&hive->ras_recovery, 0); > amdgpu_put_xgmi_hive(hive); > } > + > + complete(&ras->gpu_reset_completion); > } > > /* alloc/realloc bps array */ > @@ -2946,7 +2950,14 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, > con->gpu_reset_flags |= reset; > } > > + reinit_completion(&con->gpu_reset_completion); > + > amdgpu_ras_reset_gpu(adev); > + > + if (!wait_for_completion_timeout(&con->gpu_reset_completion, > + msecs_to_jiffies(MAX_GPU_RESET_COMPLETION_TIME))) > + dev_err(adev->dev, "Waiting for GPU to complete reset timeout! reset:0x%x\n", > + reset); Are there any looks taken here which the GPU reset might need as well? Regards, Christian. > } > > return 0; > @@ -3072,6 +3083,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) > } > } > > + init_completion(&con->gpu_reset_completion); > mutex_init(&con->page_rsv_lock); > INIT_KFIFO(con->poison_fifo); > mutex_init(&con->page_retirement_lock); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h > index 103436bb650e..d5ddd0ca5de1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h > @@ -537,6 +537,7 @@ struct amdgpu_ras { > DECLARE_KFIFO(poison_fifo, struct ras_poison_msg, AMDGPU_RAS_POISON_FIFO_SIZE); > struct ras_ecc_log_info umc_ecc_log; > struct delayed_work page_retirement_dwork; > + struct completion gpu_reset_completion; > > /* Fatal error detected flag */ > atomic_t fed;