From: "Khatri, Sunil" <sunil.khatri@amd.com>
To: boyuan.zhang@amd.com, amd-gfx@lists.freedesktop.org,
leo.liu@amd.com, christian.koenig@amd.com,
alexander.deucher@amd.com
Subject: Re: [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance
Date: Tue, 22 Oct 2024 14:26:58 +0530 [thread overview]
Message-ID: <13fb4b4c-7a32-a336-8e37-8d95c72552b7@amd.com> (raw)
In-Reply-To: <20241017132053.53214-30-boyuan.zhang@amd.com>
[-- Attachment #1: Type: text/plain, Size: 18046 bytes --]
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com
<mailto:christian.koenig@amd.com>>
On 10/17/2024 6:50 PM, boyuan.zhang@amd.com wrote:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Perform dump_ip_state only for the instance of the current vcn IP block,
> instead of perform it for all vcn instances.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 27 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 +++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 35 ++++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 31 +++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 27 +++++++++----------
> 8 files changed, 112 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 9255bcfc6c3d..27e0f206c9dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1964,7 +1964,8 @@ static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
> @@ -1972,21 +1973,19 @@ static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 94f000ed4895..665b749c5ac0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -2072,7 +2072,8 @@ static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
> @@ -2080,21 +2081,19 @@ static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 7c9a0169215e..5332b2903ce1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1946,7 +1946,8 @@ static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
> @@ -1954,21 +1955,19 @@ static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
Since this for loop is removed which dump for each instances,clear my
understanding here, there are multiple ip_blocks for vcn now and
ip_block->instance is 0, 1, 2, 3 etc representing one instance ?
Assuming the use case of 2 instances so first time when
vcn_v2_5_dump_ip_state is called it will comes with ip_block->instance =
0 and then 1 and 2 in sequence as we are dumping that information in
loop and storing in coredump in that sequence only.
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], inst));
> Storage we have linear to accomodate each vcn instance. So we need to make sure that when dump is called for instance sequentially we are adding values in vcn.ip_dump in same order so print should give right value else there could be a mismatch based on existing logic. Please try to cause a dump and hack around the code so is_powered is bypassed and we dump the values for each instance thats the only way to see if its working fine.
By looking at the code it seems it should work but there are some vcn
variable which i am not so sure in new design. Also patch for dump
should come first and then print to reverse the order of 28 and 29 patch.
But testing is needed to make sure its working fine.
Regards
Sunil khatri
> }
>
> static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 061c958700d8..40a3d29d4e71 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -2269,7 +2269,8 @@ static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
> @@ -2277,21 +2278,19 @@ static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index fdf346bf3e34..3b2f4f1e0939 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -2177,7 +2177,8 @@ static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
> @@ -2185,22 +2186,20 @@ static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
> - i));
> - }
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j],
> + inst));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index daaf2fb6b3e5..be03d31cb206 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1757,7 +1757,8 @@ static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off, inst_id;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> @@ -1765,23 +1766,21 @@ static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> -
> - inst_id = GET_INST(VCN, i);
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
> - inst_id));
> - }
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
> +
> + inst_id = GET_INST(VCN, inst);
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
> + inst_id));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index ff8db22b9614..43b1f3d06157 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -1638,7 +1638,8 @@ static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct d
> static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
> @@ -1646,22 +1647,20 @@ static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> -
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
> - i));
> - }
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j],
> + inst));
> }
>
> static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index c83a5c09f410..65554c4e86cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -1365,7 +1365,8 @@ static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm
> static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
> - int i, j;
> + int inst = ip_block->instance;
> + int j;
> bool is_powered;
> uint32_t inst_off;
> uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
> @@ -1373,21 +1374,19 @@ static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
> if (!adev->vcn.ip_dump)
> return;
>
> - for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> - if (adev->vcn.harvest_config & (1 << i))
> - continue;
> + if (adev->vcn.harvest_config & (1 << inst))
> + return;
>
> - inst_off = i * reg_count;
> - /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> - adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> - is_powered = (adev->vcn.ip_dump[inst_off] &
> - UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> + inst_off = inst * reg_count;
> + /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
> + is_powered = (adev->vcn.ip_dump[inst_off] &
> + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>
> - if (is_powered)
> - for (j = 1; j < reg_count; j++)
> - adev->vcn.ip_dump[inst_off + j] =
> - RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
> - }
> + if (is_powered)
> + for (j = 1; j < reg_count; j++)
> + adev->vcn.ip_dump[inst_off + j] =
> + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], inst));
> }
>
> static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
[-- Attachment #2: Type: text/html, Size: 18708 bytes --]
next prev parent reply other threads:[~2024-10-22 8:57 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-17 13:20 [PATCH 00/32] Separating vcn power management by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 01/32] drm/amd/pm: add inst to dpm_set_vcn_enable boyuan.zhang
2024-10-17 13:20 ` [PATCH 02/32] drm/amd/pm: power up or down vcn by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 03/32] drm/amd/pm: add inst to smu_dpm_set_vcn_enable boyuan.zhang
2024-10-17 13:20 ` [PATCH 04/32] drm/amd/pm: add inst to set_powergating_by_smu boyuan.zhang
2024-10-17 13:20 ` [PATCH 05/32] drm/amd/pm: add inst to dpm_set_powergating_by_smu boyuan.zhang
2024-10-17 13:20 ` [PATCH 06/32] add inst to amdgpu_dpm_enable_vcn boyuan.zhang
2024-10-17 13:20 ` [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
2024-10-22 7:42 ` Khatri, Sunil
2024-10-25 2:46 ` Boyuan Zhang
2024-10-17 13:20 ` [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state boyuan.zhang
2024-10-22 7:58 ` Khatri, Sunil
2024-10-25 2:48 ` Boyuan Zhang
2024-10-17 13:20 ` [PATCH 09/32] drm/amdgpu: track instances of the same IP block boyuan.zhang
2024-10-17 13:20 ` [PATCH 10/32] drm/amdgpu: move per inst variables to amdgpu_vcn_inst boyuan.zhang
2024-10-17 13:20 ` [PATCH 11/32] drm/amdgpu/vcn: separate gating state by instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 12/32] drm/amdgpu: power vcn 2_5 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 13/32] drm/amdgpu: power vcn 3_0 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 14/32] drm/amdgpu: power vcn 4_0 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 15/32] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 16/32] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 17/32] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
2024-10-17 13:20 ` [PATCH 18/32] drm/amdgpu/vcn: separate idle work " boyuan.zhang
2024-10-17 13:20 ` [PATCH 19/32] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
2024-10-17 13:20 ` [PATCH 20/32] drm/amdgpu: early_init for each " boyuan.zhang
2024-10-17 13:20 ` [PATCH 21/32] drm/amdgpu: sw_init " boyuan.zhang
2024-10-17 13:20 ` [PATCH 22/32] drm/amdgpu: sw_fini " boyuan.zhang
2024-10-28 19:40 ` Alex Deucher
2024-10-17 13:20 ` [PATCH 23/32] drm/amdgpu: hw_init " boyuan.zhang
2024-10-17 13:20 ` [PATCH 24/32] drm/amdgpu: suspend " boyuan.zhang
2024-10-17 13:20 ` [PATCH 25/32] drm/amdgpu: resume " boyuan.zhang
2024-10-17 13:20 ` [PATCH 26/32] drm/amdgpu: setup_ucode " boyuan.zhang
2024-10-17 13:20 ` [PATCH 27/32] drm/amdgpu: set funcs " boyuan.zhang
2024-10-17 13:20 ` [PATCH 28/32] drm/amdgpu: print_ip_state " boyuan.zhang
2024-10-22 8:40 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 29/32] drm/amdgpu: dump_ip_state " boyuan.zhang
2024-10-22 8:56 ` Khatri, Sunil [this message]
2024-10-22 8:59 ` Khatri, Sunil
2024-10-22 12:37 ` Khatri, Sunil
2024-10-17 13:20 ` [PATCH 30/32] drm/amdgpu: wait_for_idle " boyuan.zhang
2024-10-17 13:20 ` [PATCH 31/32] drm/amdgpu: is_idle " boyuan.zhang
2024-10-17 13:20 ` [PATCH 32/32] drm/amdgpu: set_powergating " boyuan.zhang
2024-10-22 6:25 ` [PATCH 00/32] Separating vcn power management by instance Christian König
2024-10-25 2:53 ` Boyuan Zhang
-- strict thread matches above, loose matches on Subject: below --
2024-10-08 21:15 boyuan.zhang
2024-10-08 21:15 ` [PATCH 29/32] drm/amdgpu: dump_ip_state for each vcn instance boyuan.zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=13fb4b4c-7a32-a336-8e37-8d95c72552b7@amd.com \
--to=sunil.khatri@amd.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=boyuan.zhang@amd.com \
--cc=christian.koenig@amd.com \
--cc=leo.liu@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox