Re: [PATCH 3/4] amd/amdgpu: add sched list to IPs with multiple run-queues

["Christian König" <christian.koenig@amd.com>]

Yeah, but you are to fast for me. I was still looking into comments for 
patch #4 :)

Christian.

Am 10.12.19 um 13:55 schrieb Nirmoy:
> Thanks Christian. That make sense, resent modified patches.
>
> On 12/10/19 12:28 PM, Christian König wrote:
>> Am 09.12.19 um 22:53 schrieb Nirmoy Das:
>>> This sched list can be passed on to entity creation routine
>>> instead of manually creating such sched list on every context creation.
>>
>> Please drop the "_list" from the names here. A list usually means a 
>> linked list and those are actually arrays.
>>
>> Additional to that amdgpu_device_init_sched_list() should probably go 
>> into amdgpu_ctx.c instead. That is actually not really device 
>> related, but more UAPI/ctx stuff.
>>
>> Apart from that looks good to me,
>> Christian.
>>
>>>
>>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c    | 69 
>>> ++++++++--------------
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++++++++++++++
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h    |  4 ++
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h   |  2 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h   |  2 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h    |  9 ++-
>>>   6 files changed, 85 insertions(+), 45 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>>> index 1d6850af9908..c1fc75299b7d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>>> @@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device 
>>> *adev,
>>>                  struct amdgpu_ctx *ctx)
>>>   {
>>>       unsigned num_entities = amdgpu_ctx_total_num_entities();
>>> -    unsigned i, j, k;
>>> +    unsigned i, j;
>>>       int r;
>>>         if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
>>> @@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct 
>>> amdgpu_device *adev,
>>>       ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
>>>         for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
>>> -        struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
>>> -        struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
>>> -        unsigned num_rings = 0;
>>> -        unsigned num_rqs = 0;
>>> +        struct drm_gpu_scheduler **sched_list;
>>> +        struct drm_gpu_scheduler *sched;
>>> +        unsigned num_scheds = 0;
>>>             switch (i) {
>>>           case AMDGPU_HW_IP_GFX:
>>> -            rings[0] = &adev->gfx.gfx_ring[0];
>>> -            num_rings = 1;
>>> +            sched_list = adev->gfx.gfx_sched_list;
>>> +            num_scheds = 1;
>>>               break;
>>>           case AMDGPU_HW_IP_COMPUTE:
>>> -            for (j = 0; j < adev->gfx.num_compute_rings; ++j)
>>> -                rings[j] = &adev->gfx.compute_ring[j];
>>> -            num_rings = adev->gfx.num_compute_rings;
>>> +            sched_list = adev->gfx.compute_sched_list;
>>> +            num_scheds = adev->gfx.num_compute_rings;
>>>               break;
>>>           case AMDGPU_HW_IP_DMA:
>>> -            for (j = 0; j < adev->sdma.num_instances; ++j)
>>> -                rings[j] = &adev->sdma.instance[j].ring;
>>> -            num_rings = adev->sdma.num_instances;
>>> +            sched_list = adev->sdma.sdma_sched_list;
>>> +            num_scheds = adev->sdma.num_instances;
>>>               break;
>>>           case AMDGPU_HW_IP_UVD:
>>> -            rings[0] = &adev->uvd.inst[0].ring;
>>> -            num_rings = 1;
>>> +            sched = &adev->uvd.inst[0].ring.sched;
>>> +            sched_list = &sched;
>>> +            num_scheds = 1;
>>>               break;
>>>           case AMDGPU_HW_IP_VCE:
>>> -            rings[0] = &adev->vce.ring[0];
>>> -            num_rings = 1;
>>> +            sched = &adev->vce.ring[0].sched;
>>> +            sched_list = &sched;
>>> +            num_scheds = 1;
>>>               break;
>>>           case AMDGPU_HW_IP_UVD_ENC:
>>> -            rings[0] = &adev->uvd.inst[0].ring_enc[0];
>>> -            num_rings = 1;
>>> +            sched = &adev->uvd.inst[0].ring_enc[0].sched;
>>> +            sched_list = &sched;
>>> +            num_scheds = 1;
>>>               break;
>>>           case AMDGPU_HW_IP_VCN_DEC:
>>> -            for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>>> -                if (adev->vcn.harvest_config & (1 << j))
>>> -                    continue;
>>> -                rings[num_rings++] = &adev->vcn.inst[j].ring_dec;
>>> -            }
>>> +            sched_list = adev->vcn.vcn_dec_sched_list;
>>> +            num_scheds = adev->vcn.num_vcn_dec_sched_list;
>>>               break;
>>>           case AMDGPU_HW_IP_VCN_ENC:
>>> -            for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>>> -                if (adev->vcn.harvest_config & (1 << j))
>>> -                    continue;
>>> -                for (k = 0; k < adev->vcn.num_enc_rings; ++k)
>>> -                    rings[num_rings++] = 
>>> &adev->vcn.inst[j].ring_enc[k];
>>> -            }
>>> +            sched_list = adev->vcn.vcn_enc_sched_list;
>>> +            num_scheds = adev->vcn.num_vcn_enc_sched_list;
>>>               break;
>>>           case AMDGPU_HW_IP_VCN_JPEG:
>>> -            for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
>>> -                if (adev->vcn.harvest_config & (1 << j))
>>> -                    continue;
>>> -                rings[num_rings++] = &adev->jpeg.inst[j].ring_dec;
>>> -            }
>>> +            sched_list = adev->jpeg.jpeg_sched_list;
>>> +            num_scheds =  adev->jpeg.num_jpeg_sched_list;
>>>               break;
>>>           }
>>>   -        for (j = 0; j < num_rings; ++j) {
>>> -            if (!rings[j]->adev)
>>> -                continue;
>>> -
>>> -            sched_list[num_rqs++] = &rings[j]->sched;
>>> -        }
>>> -
>>>           for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
>>>               r = drm_sched_entity_init(&ctx->entities[i][j].entity,
>>>                             priority, sched_list,
>>> -                          num_rqs, &ctx->guilty);
>>> +                          num_scheds, &ctx->guilty);
>>>           if (r)
>>>               goto error_cleanup_entities;
>>>       }
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index cf4953c4e2cf..f973b61a26da 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -2738,6 +2738,48 @@ static int 
>>> amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
>>>       return ret;
>>>   }
>>>   +static void amdgpu_device_init_sched_list(struct amdgpu_device 
>>> *adev)
>>> +{
>>> +    int i, j;
>>> +
>>> +    for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
>>> +        adev->gfx.gfx_sched_list[i] = &adev->gfx.gfx_ring[i].sched;
>>> +        adev->gfx.num_gfx_sched_list++;
>>> +    }
>>> +
>>> +    for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>>> +        adev->gfx.compute_sched_list[i] = 
>>> &adev->gfx.compute_ring[i].sched;
>>> +        adev->gfx.num_compute_sched_list++;
>>> +    }
>>> +
>>> +    for (i = 0; i < adev->sdma.num_instances; i++) {
>>> +        adev->sdma.sdma_sched_list[i] = 
>>> &adev->sdma.instance[i].ring.sched;
>>> +        adev->sdma.num_sdma_sched_list++;
>>> +    }
>>> +
>>> +    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>> +        if (adev->vcn.harvest_config & (1 << i))
>>> +            continue;
>>> + adev->vcn.vcn_dec_sched_list[adev->vcn.num_vcn_dec_sched_list++] =
>>> +            &adev->vcn.inst[i].ring_dec.sched;
>>> +    }
>>> +
>>> +    for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>> +        if (adev->vcn.harvest_config & (1 << i))
>>> +            continue;
>>> +        for (j = 0; j < adev->vcn.num_enc_rings; ++j)
>>> + adev->vcn.vcn_enc_sched_list[adev->vcn.num_vcn_enc_sched_list++] =
>>> +                &adev->vcn.inst[i].ring_enc[j].sched;
>>> +    }
>>> +
>>> +    for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
>>> +        if (adev->vcn.harvest_config & (1 << i))
>>> +            continue;
>>> + adev->jpeg.jpeg_sched_list[adev->jpeg.num_jpeg_sched_list++] =
>>> +            &adev->jpeg.inst[i].ring_dec.sched;
>>> +    }
>>> +}
>>> +
>>>   /**
>>>    * amdgpu_device_init - initialize the driver
>>>    *
>>> @@ -3024,6 +3066,8 @@ int amdgpu_device_init(struct amdgpu_device 
>>> *adev,
>>>           goto failed;
>>>       }
>>>   +    amdgpu_device_init_sched_list(adev);
>>> +
>>>       adev->accel_working = true;
>>>         amdgpu_vm_check_compute_bug(adev);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> index 0ae0a2715b0d..b2264d4cd510 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>>> @@ -269,8 +269,12 @@ struct amdgpu_gfx {
>>>       bool                me_fw_write_wait;
>>>       bool                cp_fw_write_wait;
>>>       struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
>>> +    struct drm_gpu_scheduler *gfx_sched_list[AMDGPU_MAX_GFX_RINGS];
>>> +    uint32_t            num_gfx_sched_list;
>>>       unsigned            num_gfx_rings;
>>>       struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
>>> +    uint32_t            num_compute_sched_list;
>>> +    struct drm_gpu_scheduler 
>>> *compute_sched_list[AMDGPU_MAX_COMPUTE_RINGS];
>>>       unsigned            num_compute_rings;
>>>       struct amdgpu_irq_src        eop_irq;
>>>       struct amdgpu_irq_src        priv_reg_irq;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
>>> index 5131a0a1bc8a..5ce6ab05eeac 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
>>> @@ -43,6 +43,8 @@ struct amdgpu_jpeg {
>>>       uint8_t    num_jpeg_inst;
>>>       struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
>>>       struct amdgpu_jpeg_reg internal;
>>> +    struct drm_gpu_scheduler 
>>> *jpeg_sched_list[AMDGPU_MAX_JPEG_INSTANCES];
>>> +    uint32_t num_jpeg_sched_list;
>>>       unsigned harvest_config;
>>>       struct delayed_work idle_work;
>>>       enum amd_powergating_state cur_state;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> index b3134655789f..0f6cb6768398 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>>> @@ -52,6 +52,8 @@ struct amdgpu_sdma_instance {
>>>     struct amdgpu_sdma {
>>>       struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
>>> +    struct drm_gpu_scheduler 
>>> *sdma_sched_list[AMDGPU_MAX_SDMA_INSTANCES];
>>> +    uint32_t            num_sdma_sched_list;
>>>       struct amdgpu_irq_src    trap_irq;
>>>       struct amdgpu_irq_src    illegal_inst_irq;
>>>       struct amdgpu_irq_src    ecc_irq;
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> index 402a5046b985..ae65cb8f07e8 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> @@ -31,6 +31,7 @@
>>>   #define AMDGPU_VCN_MAX_ENC_RINGS    3
>>>     #define AMDGPU_MAX_VCN_INSTANCES    2
>>> +#define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * 
>>> AMDGPU_MAX_VCN_INSTANCES
>>>     #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
>>>   #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
>>> @@ -186,8 +187,12 @@ struct amdgpu_vcn {
>>>       uint32_t        *dpg_sram_curr_addr;
>>>         uint8_t    num_vcn_inst;
>>> -    struct amdgpu_vcn_inst    inst[AMDGPU_MAX_VCN_INSTANCES];
>>> -    struct amdgpu_vcn_reg    internal;
>>> +    struct amdgpu_vcn_inst inst[AMDGPU_MAX_VCN_INSTANCES];
>>> +    struct amdgpu_vcn_reg     internal;
>>> +    struct drm_gpu_scheduler 
>>> *vcn_enc_sched_list[AMDGPU_MAX_VCN_ENC_RINGS];
>>> +    struct drm_gpu_scheduler 
>>> *vcn_dec_sched_list[AMDGPU_MAX_VCN_INSTANCES];
>>> +    uint32_t         num_vcn_enc_sched_list;
>>> +    uint32_t         num_vcn_dec_sched_list;
>>>         unsigned    harvest_config;
>>>       int (*pause_dpg_mode)(struct amdgpu_device *adev,
>>

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