From: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH v2 7/7] drm/amd/pp: Add update_avfs call when set_power_state
Date: Fri, 19 Jan 2018 16:10:11 +0800 [thread overview]
Message-ID: <1516349411-18102-8-git-send-email-Rex.Zhu@amd.com> (raw)
In-Reply-To: <1516349411-18102-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
when Overdrive voltage, need to disable AVFS.
when OverDriv engine clock, need to recalculate
AVFS voltage by disable/enable avfs feature.
Change-Id: I8545becd405949e80d8ced05d6b61ac65f71010f
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 85 ++++++++++++++++--------
1 file changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index cab1cf4..54f569c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
};
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,58 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (enable) {
+ if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_EnableAvfs),
+ "Failed to enable AVFS!",
+ return -EINVAL);
+ }
+ } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_DisableAvfs),
+ "Failed to disable AVFS!",
+ return -EINVAL);
+ }
+
+ return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+ smu7_avfs_control(hwmgr, false);
+ } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+ smu7_avfs_control(hwmgr, false);
+ smu7_avfs_control(hwmgr, true);
+ } else {
+ smu7_avfs_control(hwmgr, true);
+ }
+
+ return 0;
+}
+
int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
@@ -3842,6 +3893,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
+ tmp_result = smu7_update_avfs(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == tmp_result),
+ "Failed to update avfs voltages!",
+ result = tmp_result);
+
tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
@@ -4626,33 +4682,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
return result;
}
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
- if (smu_data == NULL)
- return -EINVAL;
-
- if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return 0;
-
- if (enable) {
- if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_EnableAvfs),
- "Failed to enable AVFS!",
- return -EINVAL);
- } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_DisableAvfs),
- "Failed to disable AVFS!",
- return -EINVAL);
-
- return 0;
-}
-
static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
--
1.9.1
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next prev parent reply other threads:[~2018-01-19 8:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-19 8:10 [PATCH v2 0/7] Add sysfs to support OverDrive feature Rex Zhu
[not found] ` <1516349411-18102-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-19 8:10 ` [PATCH v2 1/7] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
2018-01-19 8:10 ` [PATCH v2 2/7] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs Rex Zhu
2018-01-19 8:10 ` [PATCH v2 3/7] drm/amd/pp: Disable OD feature if VBIOS limits Rex Zhu
[not found] ` <1516349411-18102-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-19 17:21 ` Alex Deucher
2018-01-19 8:10 ` [PATCH v2 4/7] drm/amd/pp: Disable OD feature on CI/Iceland Rex Zhu
[not found] ` <1516349411-18102-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-19 17:23 ` Alex Deucher
2018-01-19 8:10 ` [PATCH v2 5/7] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
[not found] ` <1516349411-18102-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-19 17:24 ` Alex Deucher
2018-01-22 4:17 ` 答复: " Quan, Evan
2018-01-19 8:10 ` [PATCH v2 6/7] drm/amd/pp: Update smu7 dpm table with OD clock/voltage Rex Zhu
[not found] ` <1516349411-18102-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-22 4:31 ` 答复: " Quan, Evan
2018-01-19 8:10 ` Rex Zhu [this message]
[not found] ` <1516349411-18102-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-22 4:57 ` 答复: [PATCH v2 7/7] drm/amd/pp: Add update_avfs call when set_power_state Quan, Evan
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