From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCH 1/5] drm/amdgpu: add system interrupt register offset header Date: Wed, 18 Jul 2018 16:39:11 -0400 Message-ID: <1531946355-17488-1-git-send-email-boyuan.zhang@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Boyuan Zhang RnJvbTogQm95dWFuIFpoYW5nIDxib3l1YW4uemhhbmdAYW1kLmNvbT4KCkFkZCBuZXcgcmVnaXN0 ZXIgb2Zmc2V0IGZvciBlbmFibGluZyBzeXN0ZW0gaW50ZXJydXB0LgoKU2lnbmVkLW9mZi1ieTog Qm95dWFuIFpoYW5nIDxib3l1YW4uemhhbmdAYW1kLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0v YW1kL2luY2x1ZGUvYXNpY19yZWcvdmNuL3Zjbl8xXzBfb2Zmc2V0LmggfCAyICsrCiAxIGZpbGUg Y2hhbmdlZCwgMiBpbnNlcnRpb25zKCspCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2Ft ZC9pbmNsdWRlL2FzaWNfcmVnL3Zjbi92Y25fMV8wX29mZnNldC5oIGIvZHJpdmVycy9ncHUvZHJt L2FtZC9pbmNsdWRlL2FzaWNfcmVnL3Zjbi92Y25fMV8wX29mZnNldC5oCmluZGV4IGZlMGNiYWEu LjIxNmE0MDEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hbWQvaW5jbHVkZS9hc2ljX3Jl Zy92Y24vdmNuXzFfMF9vZmZzZXQuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2luY2x1ZGUv YXNpY19yZWcvdmNuL3Zjbl8xXzBfb2Zmc2V0LmgKQEAgLTMwNyw2ICszMDcsOCBAQAogI2RlZmlu ZSBtbVVWRF9MTUlfQ1RSTDJfQkFTRV9JRFggICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDEKICNkZWZpbmUgbW1VVkRf TUFTVElOVF9FTiAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAweDA1NDAKICNkZWZpbmUgbW1VVkRfTUFT VElOVF9FTl9CQVNFX0lEWCAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAxCisjZGVmaW5lIG1tVVZEX1NZU19JTlRfRU4g ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgMHgwNTQxCisjZGVmaW5lIG1tVVZEX1NZU19JTlRfRU5fQkFT RV9JRFggICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgMQogI2RlZmluZSBtbUpQRUdfQ0dDX0NUUkwgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIDB4MDU2NQogI2RlZmluZSBtbUpQRUdfQ0dDX0NUUkxfQkFTRV9JRFggICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIDEKICNkZWZpbmUgbW1VVkRfTE1JX0NUUkwgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAw eDA1NjYKLS0gCjIuNy40CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwphbWQtZ2Z4IG1haWxpbmcgbGlzdAphbWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9y ZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK