From mboxrd@z Thu Jan 1 00:00:00 1970 From: Subject: [PATCH 2/5] drm/amdgpu: add system interrupt mask for jrbc Date: Wed, 18 Jul 2018 16:39:12 -0400 Message-ID: <1531946355-17488-2-git-send-email-boyuan.zhang@amd.com> References: <1531946355-17488-1-git-send-email-boyuan.zhang@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1531946355-17488-1-git-send-email-boyuan.zhang-5C7GfCeVMHo@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Boyuan Zhang RnJvbTogQm95dWFuIFpoYW5nIDxib3l1YW4uemhhbmdAYW1kLmNvbT4KCkFkZCBuZXcgbWFzayBm b3IgZW5hYmxpbmcgc3lzdGVtIGludGVycnVwdCBmb3IganJiYy4KClNpZ25lZC1vZmYtYnk6IEJv eXVhbiBaaGFuZyA8Ym95dWFuLnpoYW5nQGFtZC5jb20+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2Ft ZC9pbmNsdWRlL2FzaWNfcmVnL3Zjbi92Y25fMV8wX3NoX21hc2suaCB8IDIgKysKIDEgZmlsZSBj aGFuZ2VkLCAyIGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vYW1k L2luY2x1ZGUvYXNpY19yZWcvdmNuL3Zjbl8xXzBfc2hfbWFzay5oIGIvZHJpdmVycy9ncHUvZHJt L2FtZC9pbmNsdWRlL2FzaWNfcmVnL3Zjbi92Y25fMV8wX3NoX21hc2suaAppbmRleCBkNmJhMjY5 Li4xMjQzODNkIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vYW1kL2luY2x1ZGUvYXNpY19y ZWcvdmNuL3Zjbl8xXzBfc2hfbWFzay5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9hbWQvaW5jbHVk ZS9hc2ljX3JlZy92Y24vdmNuXzFfMF9zaF9tYXNrLmgKQEAgLTk4Miw2ICs5ODIsOCBAQAogI2Rl ZmluZSBVVkRfTUFTVElOVF9FTl9fVkNQVV9FTl9NQVNLICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAweDAwMDAw MDAyTAogI2RlZmluZSBVVkRfTUFTVElOVF9FTl9fU1lTX0VOX01BU0sgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAweDAwMDAwMDA0TAogI2RlZmluZSBVVkRfTUFTVElOVF9FTl9fSU5UX09WRVJSVU5fTUFTSyAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAweDAwN0ZGRkYwTAorLy9VVkRfU1lTX0lOVF9FTgorI2RlZmluZSBVVkRfU1lT X0lOVF9FTl9fVVZEX0pSQkNfRU5fTUFTSyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAweDAwMDAwMDEwTAogLy9KUEVH X0NHQ19DVFJMCiAjZGVmaW5lIEpQRUdfQ0dDX0NUUkxfX0RZTl9DTE9DS19NT0RFX19TSElGVCAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIDB4MAogI2RlZmluZSBKUEVHX0NHQ19DVFJMX19KUEVHMl9NT0RFX19TSElGVCAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAweDEKLS0gCjIuNy40CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwphbWQtZ2Z4IG1haWxpbmcgbGlzdAphbWQtZ2Z4QGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2Ft ZC1nZngK