[PATCH 9/9] drm/amdgpu: Remove sriov check when insert ce/de meta_data

Rex Zhu
2018-12-06T11:32:37Z

to support cp gfx mid-command buffer preemption in baremetal

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 15 ++++++++++-----
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++++++++++-----
2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 3ac2d8f..ccc461f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6123,7 +6123,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,

control |= ib->length_dw | (vmid << 24);

- if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+ if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
control |= INDIRECT_BUFFER_PRE_ENB(1);

if (!(ib->flags & AMDGPU_IB_FLAG_CE))
@@ -6392,8 +6392,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring,
{
uint32_t dw2 = 0;

- if (amdgpu_sriov_vf(ring->adev))
- gfx_v8_0_ring_emit_ce_meta(ring, job);
+ gfx_v8_0_ring_emit_ce_meta(ring, job);

dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -7194,8 +7193,11 @@ static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring,
struct vi_ce_ib_state_chained_ib chained;
} ce_payload = {};

+ if (!job)
+ return;
+
if (ring->adev->virt.chained_ib_support) {
- ce_payload_addr = amdgpu_csa_vaddr(ring->adev, 1) +
+ ce_payload_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job) +
offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
} else {
@@ -7224,7 +7226,10 @@ static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring,
struct vi_de_ib_state_chained_ib chained;
} de_payload = {};

- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ if (!job)
+ return;
+
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
gds_addr = csa_addr + 4096;
if (ring->adev->virt.chained_ib_support) {
de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dd2d535..6d38834 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4063,7 +4063,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,

control |= ib->length_dw | (vmid << 24);

- if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+ if (ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
control |= INDIRECT_BUFFER_PRE_ENB(1);

if (!(ib->flags & AMDGPU_IB_FLAG_CE))
@@ -4327,8 +4327,11 @@ static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring,
uint64_t csa_addr;
int cnt;

+ if (!job)
+ return;
+
cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);

amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
@@ -4347,7 +4350,10 @@ static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring,
uint64_t csa_addr, gds_addr;
int cnt;

- csa_addr = amdgpu_csa_vaddr(ring->adev, 1);
+ if (!job)
+ return;
+
+ csa_addr = AMDGPU_JOB_GET_CSA_MC_ADDR(job);
gds_addr = csa_addr + 4096;
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
@@ -4375,8 +4381,7 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring,
{
uint32_t dw2 = 0;

- if (amdgpu_sriov_vf(ring->adev))
- gfx_v9_0_ring_emit_ce_meta(ring, job);
+ gfx_v9_0_ring_emit_ce_meta(ring, job);

gfx_v9_0_ring_emit_tmz(ring, true);