AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: sunpeng.li-5C7GfCeVMHo@public.gmane.org,
	Dmytro Laktyushkin
	<Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 18/45] drm/amd/display: update DCN dml calcs
Date: Tue, 11 Dec 2018 17:57:24 -0500	[thread overview]
Message-ID: <1544569071-7114-19-git-send-email-sunpeng.li@amd.com> (raw)
In-Reply-To: <1544569071-7114-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

DV have made updates to DCN dml which we need to pull in

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   7 --
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   2 +-
 .../drm/amd/display/dc/dml/display_mode_structs.h  | 107 ++-------------------
 .../amd/display/dc/dml/dml1_display_rq_dlg_calc.c  |   4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |   4 +-
 5 files changed, 11 insertions(+), 113 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index cd88cec..446ee48 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -290,41 +290,34 @@ static void pipe_ctx_to_e2e_pipe_params (
 	switch (pipe->plane_state->tiling_info.gfx9.swizzle) {
 	/* for 4/8/16 high tiles */
 	case DC_SW_LINEAR:
-		input->src.is_display_sw = 1;
 		input->src.macro_tile_size = dm_4k_tile;
 		break;
 	case DC_SW_4KB_S:
 	case DC_SW_4KB_S_X:
-		input->src.is_display_sw = 0;
 		input->src.macro_tile_size = dm_4k_tile;
 		break;
 	case DC_SW_64KB_S:
 	case DC_SW_64KB_S_X:
 	case DC_SW_64KB_S_T:
-		input->src.is_display_sw = 0;
 		input->src.macro_tile_size = dm_64k_tile;
 		break;
 	case DC_SW_VAR_S:
 	case DC_SW_VAR_S_X:
-		input->src.is_display_sw = 0;
 		input->src.macro_tile_size = dm_256k_tile;
 		break;
 
 	/* For 64bpp 2 high tiles */
 	case DC_SW_4KB_D:
 	case DC_SW_4KB_D_X:
-		input->src.is_display_sw = 1;
 		input->src.macro_tile_size = dm_4k_tile;
 		break;
 	case DC_SW_64KB_D:
 	case DC_SW_64KB_D_X:
 	case DC_SW_64KB_D_T:
-		input->src.is_display_sw = 1;
 		input->src.macro_tile_size = dm_64k_tile;
 		break;
 	case DC_SW_VAR_D:
 	case DC_SW_VAR_D_X:
-		input->src.is_display_sw = 1;
 		input->src.macro_tile_size = dm_256k_tile;
 		break;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 6ab1ca2..83447cd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -70,7 +70,7 @@
 const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
 	.rob_buffer_size_kbytes = 64,
 	.det_buffer_size_kbytes = 164,
-	.dpte_buffer_size_in_pte_reqs = 42,
+	.dpte_buffer_size_in_pte_reqs_luma = 42,
 	.dpp_output_buffer_pixels = 2560,
 	.opp_output_buffer_lines = 1,
 	.pixel_chunk_size_kbytes = 8,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 5dd0452..391183e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -30,22 +30,15 @@ typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st;
 typedef struct _vcs_dpi_ip_params_st ip_params_st;
 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st;
 typedef struct _vcs_dpi_display_output_params_st display_output_params_st;
-typedef struct _vcs_dpi_display_bandwidth_st display_bandwidth_st;
 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st;
 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st;
 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st;
 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st;
 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st;
 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st;
-typedef struct _vcs_dpi_dchub_buffer_sizing_st dchub_buffer_sizing_st;
-typedef struct _vcs_dpi_watermarks_perf_st watermarks_perf_st;
-typedef struct _vcs_dpi_cstate_pstate_watermarks_st cstate_pstate_watermarks_st;
-typedef struct _vcs_dpi_wm_calc_pipe_params_st wm_calc_pipe_params_st;
-typedef struct _vcs_dpi_vratio_pre_st vratio_pre_st;
 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st;
 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st;
 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st;
-typedef struct _vcs_dpi_display_cur_rq_dlg_params_st display_cur_rq_dlg_params_st;
 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st;
 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st;
 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st;
@@ -55,8 +48,6 @@ typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st;
 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st;
 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
-typedef struct _vcs_dpi_display_dlg_prefetch_param_st display_dlg_prefetch_param_st;
-typedef struct _vcs_dpi_display_pipe_clock_st display_pipe_clock_st;
 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
 
 struct _vcs_dpi_voltage_scaling_st {
@@ -111,8 +102,6 @@ struct _vcs_dpi_soc_bounding_box_st {
 	double xfc_bus_transport_time_us;
 	double xfc_xbuf_latency_tolerance_us;
 	int use_urgent_burst_bw;
-	double max_hscl_ratio;
-	double max_vscl_ratio;
 	unsigned int num_states;
 	struct _vcs_dpi_voltage_scaling_st clock_limits[8];
 };
@@ -129,7 +118,8 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int odm_capable;
 	unsigned int rob_buffer_size_kbytes;
 	unsigned int det_buffer_size_kbytes;
-	unsigned int dpte_buffer_size_in_pte_reqs;
+	unsigned int dpte_buffer_size_in_pte_reqs_luma;
+	unsigned int dpte_buffer_size_in_pte_reqs_chroma;
 	unsigned int pde_proc_buffer_size_64k_reqs;
 	unsigned int dpp_output_buffer_pixels;
 	unsigned int opp_output_buffer_lines;
@@ -192,7 +182,6 @@ struct _vcs_dpi_display_xfc_params_st {
 struct _vcs_dpi_display_pipe_source_params_st {
 	int source_format;
 	unsigned char dcc;
-	unsigned int dcc_override;
 	unsigned int dcc_rate;
 	unsigned char dcc_use_global;
 	unsigned char vm;
@@ -205,7 +194,6 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	int source_scan;
 	int sw_mode;
 	int macro_tile_size;
-	unsigned char is_display_sw;
 	unsigned int viewport_width;
 	unsigned int viewport_height;
 	unsigned int viewport_y_y;
@@ -252,16 +240,10 @@ struct _vcs_dpi_display_output_params_st {
 	int output_bpc;
 	int output_type;
 	int output_format;
-	int output_standard;
 	int dsc_slices;
 	struct writeback_st wb;
 };
 
-struct _vcs_dpi_display_bandwidth_st {
-	double total_bw_consumed_gbps;
-	double guaranteed_urgent_return_bw_gbps;
-};
-
 struct _vcs_dpi_scaler_ratio_depth_st {
 	double hscl_ratio;
 	double vscl_ratio;
@@ -300,11 +282,9 @@ struct _vcs_dpi_display_pipe_dest_params_st {
 	unsigned int vupdate_width;
 	unsigned int vready_offset;
 	unsigned char interlaced;
-	unsigned char underscan;
 	double pixel_rate_mhz;
 	unsigned char synchronized_vblank_all_planes;
 	unsigned char otg_inst;
-	unsigned char odm_split_cnt;
 	unsigned char odm_combine;
 	unsigned char use_maximum_vstartup;
 };
@@ -331,65 +311,6 @@ struct _vcs_dpi_display_e2e_pipe_params_st {
 	display_clocks_and_cfg_st clks_cfg;
 };
 
-struct _vcs_dpi_dchub_buffer_sizing_st {
-	unsigned int swath_width_y;
-	unsigned int swath_height_y;
-	unsigned int swath_height_c;
-	unsigned int detail_buffer_size_y;
-};
-
-struct _vcs_dpi_watermarks_perf_st {
-	double stutter_eff_in_active_region_percent;
-	double urgent_latency_supported_us;
-	double non_urgent_latency_supported_us;
-	double dram_clock_change_margin_us;
-	double dram_access_eff_percent;
-};
-
-struct _vcs_dpi_cstate_pstate_watermarks_st {
-	double cstate_exit_us;
-	double cstate_enter_plus_exit_us;
-	double pstate_change_us;
-};
-
-struct _vcs_dpi_wm_calc_pipe_params_st {
-	unsigned int num_dpp;
-	int voltage;
-	int output_type;
-	double dcfclk_mhz;
-	double socclk_mhz;
-	double dppclk_mhz;
-	double pixclk_mhz;
-	unsigned char interlace_en;
-	unsigned char pte_enable;
-	unsigned char dcc_enable;
-	double dcc_rate;
-	double bytes_per_pixel_c;
-	double bytes_per_pixel_y;
-	unsigned int swath_width_y;
-	unsigned int swath_height_y;
-	unsigned int swath_height_c;
-	unsigned int det_buffer_size_y;
-	double h_ratio;
-	double v_ratio;
-	unsigned int h_taps;
-	unsigned int h_total;
-	unsigned int v_total;
-	unsigned int v_active;
-	unsigned int e2e_index;
-	double display_pipe_line_delivery_time;
-	double read_bw;
-	unsigned int lines_in_det_y;
-	unsigned int lines_in_det_y_rounded_down_to_swath;
-	double full_det_buffering_time;
-	double dcfclk_deepsleep_mhz_per_plane;
-};
-
-struct _vcs_dpi_vratio_pre_st {
-	double vratio_pre_l;
-	double vratio_pre_c;
-};
-
 struct _vcs_dpi_display_data_rq_misc_params_st {
 	unsigned int full_swath_bytes;
 	unsigned int stored_swath_bytes;
@@ -423,16 +344,9 @@ struct _vcs_dpi_display_data_rq_dlg_params_st {
 	unsigned int meta_bytes_per_row_ub;
 };
 
-struct _vcs_dpi_display_cur_rq_dlg_params_st {
-	unsigned char enable;
-	unsigned int swath_height;
-	unsigned int req_per_line;
-};
-
 struct _vcs_dpi_display_rq_dlg_params_st {
 	display_data_rq_dlg_params_st rq_l;
 	display_data_rq_dlg_params_st rq_c;
-	display_cur_rq_dlg_params_st rq_cur0;
 };
 
 struct _vcs_dpi_display_rq_sizing_params_st {
@@ -498,6 +412,10 @@ struct _vcs_dpi_display_dlg_regs_st {
 	unsigned int xfc_reg_remote_surface_flip_latency;
 	unsigned int xfc_reg_prefetch_margin;
 	unsigned int dst_y_delta_drq_limit;
+	unsigned int refcyc_per_vm_group_vblank;
+	unsigned int refcyc_per_vm_group_flip;
+	unsigned int refcyc_per_vm_req_vblank;
+	unsigned int refcyc_per_vm_req_flip;
 };
 
 struct _vcs_dpi_display_ttu_regs_st {
@@ -556,19 +474,6 @@ struct _vcs_dpi_display_dlg_sys_params_st {
 	unsigned int total_flip_bytes;
 };
 
-struct _vcs_dpi_display_dlg_prefetch_param_st {
-	double prefetch_bw;
-	unsigned int flip_bytes;
-};
-
-struct _vcs_dpi_display_pipe_clock_st {
-	double dcfclk_mhz;
-	double dispclk_mhz;
-	double socclk_mhz;
-	double dscclk_mhz[6];
-	double dppclk_mhz[6];
-};
-
 struct _vcs_dpi_display_arb_params_st {
 	int max_req_outstanding;
 	int min_req_outstanding;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
index c2037da..a8b233e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c
@@ -459,7 +459,7 @@ static void dml1_rq_dlg_get_row_heights(
 	/* dpte   */
 	/* ------ */
 	log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
 
 	log2_vmpg_height = 0;
 	log2_vmpg_width = 0;
@@ -776,7 +776,7 @@ static void get_surf_rq_param(
 	/* dpte   */
 	/* ------ */
 	log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
-	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
+	dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
 
 	log2_vmpg_height = 0;
 	log2_vmpg_width = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 06df02d..da89c2e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -31,7 +31,7 @@
 #include "dml/display_mode_structs.h"
 
 struct dchub_init_data;
-struct cstate_pstate_watermarks_st1 {
+struct cstate_pstate_watermarks_st {
 	uint32_t cstate_exit_ns;
 	uint32_t cstate_enter_plus_exit_ns;
 	uint32_t pstate_change_ns;
@@ -40,7 +40,7 @@ struct cstate_pstate_watermarks_st1 {
 struct dcn_watermarks {
 	uint32_t pte_meta_urgent_ns;
 	uint32_t urgent_ns;
-	struct cstate_pstate_watermarks_st1 cstate_pstate;
+	struct cstate_pstate_watermarks_st cstate_pstate;
 };
 
 struct dcn_watermark_set {
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2018-12-11 22:57 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-11 22:57 [PATCH 00/45] DC Patches Dec 11, 2018 sunpeng.li-5C7GfCeVMHo
     [not found] ` <1544569071-7114-1-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2018-12-11 22:57   ` [PATCH 01/45] drm/amd/display: 3.2.09 sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 02/45] drm/amd/display: Add a PP_SMU_VER_MAX enum sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 03/45] drm/amd/display: Expose hubp1_vready_workaround function sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 04/45] drm/amd/display: Fix runtime errors for diagnostic tests sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 05/45] drm/amd/display: fix surface update sequence sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 06/45] drm/amd/display: Add pixel clock values to dtn logs sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 07/45] drm/amd/display: Remove some extra braces sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 08/45] drm/amd/display: implement dc_init_callbacks to assign callback pointers after dc_create sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 09/45] drm/amd/display: add plane size change check condition sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 10/45] drm/amd/display: Fix issue with VLine interrupt not firing sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 11/45] drm/amd/display: update bw formula to v252 sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 12/45] drm/amd/display: Add debug option to force fclk request sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 13/45] drm/amd/display: remove sink reference in dc_stream_state sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 14/45] drm/amd/display: Remove unused headers sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 15/45] drm/amd/display: Detach backlight from stream sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 16/45] drm/amd/display: Raise dispclk value for Polaris sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 17/45] drm/amd/display: Warn instead of error on REG_WAIT timeout sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` sunpeng.li-5C7GfCeVMHo [this message]
2018-12-11 22:57   ` [PATCH 19/45] drm/amd/display: fix YCbCr420 blank color sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 20/45] drm/amd/display: Wait edp HPD to high in detect_sink sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 21/45] drm/amd/display: Don't skip link training for empty dongle sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 22/45] drm/amd/display: add stream ID and otg instance in dc_stream_state sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 23/45] drm/amd/display: Add backlight pwm debugfs sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 24/45] drm/amd/display: 3.2.10 sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 25/45] drm/amd/display: Remove stream_status->link sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 26/45] drm/amd/display: Add retry to read ddc_clock pin sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 27/45] drm/amd/display: Fix driver load crash in amdgpu_dm sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 28/45] drm/amd/display: Minor code cleanup sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 29/45] drm/amd/display: Use 100 Hz precision for pipe pixel clocks sunpeng.li-5C7GfCeVMHo
     [not found]     ` <1544569071-7114-30-git-send-email-sunpeng.li-5C7GfCeVMHo@public.gmane.org>
2018-12-12  8:19       ` Christian König
     [not found]         ` <2cf9b879-6c37-6879-e4bb-12fb309f8e94-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-12-12 18:29           ` Chalmers, Kenneth
2018-12-11 22:57   ` [PATCH 30/45] drm/amd/display: Improve logging of validation failures during atomic_check sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 31/45] drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20 sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 32/45] drm/amd/display: Add functionality to get XGMI SS info sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 33/45] drm/amd/display: Use local variable instead of caching global sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 34/45] drm/amd/display: Compensate for XGMI SS downspread on dprefclk sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 35/45] drm/amd/display: 3.2.11 sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 36/45] drm/amd/display: Start using the new pp_smu interface sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 37/45] drm/amd/display: Fix bug with not updating VSP infoframe sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 38/45] drm/amd/display: add dsclk to pipe bw struct sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 39/45] drm/amd/display: move AYCrCb8888 format to video section sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 40/45] drm/amd/display: Don't log error if we have no connectors sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 41/45] drm/amd/display: verify lane status before exiting verify link cap sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 42/45] drm/amd/display: Optimize passive update planes sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 43/45] drm/amd/display: Expand set_pixel_clock debug log message sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 44/45] drm/amd/display: validate extended dongle caps sunpeng.li-5C7GfCeVMHo
2018-12-11 22:57   ` [PATCH 45/45] drm/amd/display: Remove unused parameter plane_states sunpeng.li-5C7GfCeVMHo

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1544569071-7114-19-git-send-email-sunpeng.li@amd.com \
    --to=sunpeng.li-5c7gfcevmho@public.gmane.org \
    --cc=Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org \
    --cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox