From: James Zhu <James.Zhu@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: jamesz@amd.com
Subject: [PATCH v2 4/4] drm/amdgpu/vcn2.5: add sync when WPTR/RPTR reset
Date: Tue, 10 Mar 2020 15:58:00 -0400 [thread overview]
Message-ID: <1583870280-13102-1-git-send-email-James.Zhu@amd.com> (raw)
In-Reply-To: <1583259391-21834-4-git-send-email-James.Zhu@amd.com>
Add vcn harware and firmware synchronization to fix race condition
issue among vcn driver, hardware and firmware
v2: WA: Add scratch 3 to sync with vcn firmware during W/R pointer reset
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 2d64ba1..9480039 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1034,6 +1034,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
+ /* Set scratch3 to start dec/enc registers reset */
+ WREG32_SOC15(UVD, i, mmUVD_SCRATCH3, 1);
+
/* programm the RB_BASE for ring buffer */
WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
lower_32_bits(ring->gpu_addr));
@@ -1059,6 +1062,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
+
+ /* Clear scratch3 to finish dec/enc registers reset */
+ WREG32_SOC15(UVD, i, mmUVD_SCRATCH3, 0);
}
return 0;
@@ -1388,8 +1394,11 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
+ /* Stall DPG before WPTR/RPTR reset */
+ WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
/* Restore */
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
+ ring->wptr = 0;
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
@@ -1397,6 +1406,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
+ ring->wptr = 0;
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
WREG32_SOC15(UVD, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
@@ -1405,6 +1415,8 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
WREG32_SOC15(UVD, inst_idx, mmUVD_RBC_RB_WPTR,
RREG32_SOC15(UVD, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
+ /* Unstall DPG */
+ WREG32_P(SOC15_REG_OFFSET(UVD, inst_idx, mmUVD_POWER_STATUS), 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
SOC15_WAIT_ON_RREG(UVD, inst_idx, mmUVD_POWER_STATUS,
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
--
2.7.4
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next prev parent reply other threads:[~2020-03-10 19:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 18:16 [PATCH 1/4] drm/amdgpu/vcn: fix race condition issue for vcn start James Zhu
2020-03-03 18:16 ` [PATCH 2/4] drm/amdgpu/vcn: fix race condition issue for dpg unpause mode switch James Zhu
2020-03-09 16:58 ` [PATCH v3 " James Zhu
2020-03-11 14:16 ` [PATCH v4 " James Zhu
2020-03-03 18:16 ` [PATCH 3/4] drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR reset James Zhu
2020-03-03 18:16 ` [PATCH 4/4] drm/amdgpu/vcn2.5: " James Zhu
2020-03-10 19:58 ` James Zhu [this message]
2020-03-10 20:03 ` [PATCH v2 4/4] drm/amdgpu/vcn2.5: add sync " Leo Liu
2020-03-03 18:44 ` [PATCH 1/4] drm/amdgpu/vcn: fix race condition issue for vcn start Christian König
2020-03-03 19:03 ` James Zhu
2020-03-03 22:48 ` James Zhu
2020-03-04 8:53 ` Christian König
2020-03-04 14:57 ` James Zhu
2020-03-04 15:03 ` Christian König
2020-03-04 15:09 ` James Zhu
2020-03-04 16:34 ` [PATCH v2 " James Zhu
2020-03-05 11:25 ` Christian König
2020-03-05 11:27 ` Christian König
2020-03-05 14:34 ` James Zhu
2020-03-09 16:57 ` [PATCH v3 " James Zhu
2020-03-11 11:30 ` Zhu, James
2020-03-11 11:38 ` Christian König
2020-03-11 14:15 ` James Zhu
2020-03-11 14:15 ` [PATCH v4 " James Zhu
2020-03-11 14:39 ` Christian König
2020-03-11 15:04 ` [PATCH v5 " James Zhu
2020-03-11 15:13 ` Christian König
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