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From: Prike Liang <Prike.Liang@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alexander.Deucher@amd.com, Prike Liang <Prike.Liang@amd.com>,
	ray.huang@amd.com
Subject: [PATCH 3/4] drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support
Date: Fri, 13 Nov 2020 14:53:16 +0800	[thread overview]
Message-ID: <1605250397-15043-3-git-send-email-Prike.Liang@amd.com> (raw)
In-Reply-To: <1605250397-15043-1-git-send-email-Prike.Liang@amd.com>

- Need skip the RLC/CP/GFX disable for let GFXOFF enter during suspend period.
- For s0i3 suspend only need suspend DCE and each IP interrupt.
- Before VBIOS POSTed check and atom HW INT need set the GPU power status change
  to D0 in the resume period, otherwise the HW will be mess up and see the SDMA hang.
- Need handle the GPU reset path during amdgpu device suspend.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f78aace..2f60b70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2650,8 +2650,10 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
 {
 	int i, r;
 
-	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
-	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+	if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) {
+		amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
+		amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+	}
 
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 		if (!adev->ip_blocks[i].status.valid)
@@ -3706,8 +3708,10 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
 
 	amdgpu_fence_driver_suspend(adev);
 
-	r = amdgpu_device_ip_suspend_phase2(adev);
-
+	if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev))
+		r = amdgpu_device_ip_suspend_phase2(adev);
+	else
+		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
 	/* evict remaining vram memory
 	 * This second call to evict vram is to evict the gart page table
 	 * using the CPU.
@@ -3738,6 +3742,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
 	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 		return 0;
 
+	if (amdgpu_acpi_is_s0ix_supported())
+		amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
+
 	/* post card */
 	if (amdgpu_device_need_post(adev)) {
 		r = amdgpu_device_asic_init(adev);
-- 
2.7.4

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  parent reply	other threads:[~2020-11-13  6:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-13  6:53 [PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine Prike Liang
2020-11-13  6:53 ` [PATCH 2/4] drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry Prike Liang
2020-11-13  6:53 ` Prike Liang [this message]
2020-11-13  6:53 ` [PATCH 4/4] drm/amd/pm: add gfx_state_change_set() for rn gfx power switch Prike Liang
2020-11-13  6:58   ` Alex Deucher
2020-11-13  8:37   ` Huang Rui
  -- strict thread matches above, loose matches on Subject: below --
2020-10-16  9:21 [PATCH 1/4] drm/amdgpu: add s0i3 capacity check for s0i3 routine Prike Liang
2020-10-16  9:21 ` [PATCH 3/4] drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support Prike Liang

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