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[2001:4c4e:24d8:e500:ac9d:aee3:e0cd:fa47]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47a9de1d910sm30844655f8f.6.2026.07.07.01.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2026 01:08:46 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org Cc: Alex Deucher , Alex Deucher Subject: Re: [PATCH 4/4] drm/amdgpu/gfx11: enable gfx pipe1 hardware support Date: Tue, 07 Jul 2026 10:08:45 +0200 Message-ID: <1961599.dNmn5OnKVQ@timur-max> In-Reply-To: <20260626204101.31172-4-alexander.deucher@amd.com> References: <20260626204101.31172-1-alexander.deucher@amd.com> <20260626204101.31172-4-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAnius 26., p=C3=A9ntek 22:41:01 k=C3=B6z=C3=A9p-eur=C3=B3pai= ny=C3=A1ri id=C5=91 Alex Deucher=20 wrote: > Enable gfx pipe1 hardware support. This is only available > on gfx11 chips using the F32 microcontroller. Chips using > the RS64 microcontroller are not able to use the second gfx > pipe. In practice this means the second pipe is only > available on APUs. This explains the stability issues > Pierre-Eric saw previously with this on Navi33. >=20 > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 22 +++++++++++++++++----- > 1 file changed, 17 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5e7d0cd85c365..c0e34519b6b= 06 > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c > @@ -51,7 +51,7 @@ > #include "mes_userqueue.h" > #include "amdgpu_userq_fence.h" >=20 > -#define GFX11_NUM_GFX_RINGS 1 > +#define GFX11_NUM_GFX_RINGS 2 > #define GFX11_MEC_HPD_SIZE 2048 >=20 > #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L > @@ -1612,7 +1612,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block > *ip_block) case IP_VERSION(11, 5, 4): > case IP_VERSION(11, 5, 6): > adev->gfx.me.num_me =3D 1; > - adev->gfx.me.num_pipe_per_me =3D 1; > + if (adev->gfx.rs64_enable) > + adev->gfx.me.num_pipe_per_me =3D 1; > + else > + adev->gfx.me.num_pipe_per_me =3D 2; > adev->gfx.me.num_queue_per_pipe =3D 2; > adev->gfx.mec.num_mec =3D 1; > adev->gfx.mec.num_pipe_per_mec =3D 4; > @@ -5355,6 +5358,7 @@ static void gfx_v11_0_ring_emit_gds_switch(struct > amdgpu_ring *ring, static int gfx_v11_0_early_init(struct amdgpu_ip_block > *ip_block) { > struct amdgpu_device *adev =3D ip_block->adev; > + int r; >=20 > switch (amdgpu_user_queue) { > case -1: > @@ -5375,6 +5379,11 @@ static int gfx_v11_0_early_init(struct > amdgpu_ip_block *ip_block) >=20 > adev->gfx.funcs =3D &gfx_v11_0_gfx_funcs; >=20 > + gfx_v11_0_set_imu_funcs(adev); > + r =3D gfx_v11_0_init_microcode(adev); > + if (r) > + return r; > + > if (adev->gfx.disable_kq) { > /* We need one GFX ring temporarily to set up > * the clear state. > @@ -5382,7 +5391,11 @@ static int gfx_v11_0_early_init(struct > amdgpu_ip_block *ip_block) adev->gfx.num_gfx_rings =3D 1; > adev->gfx.num_compute_rings =3D 0; > } else { > - adev->gfx.num_gfx_rings =3D GFX11_NUM_GFX_RINGS; > + /* rs64 only supports one gfx pipe */ > + if (adev->gfx.rs64_enable) > + adev->gfx.num_gfx_rings =3D 1; > + else > + adev->gfx.num_gfx_rings =3D=20 GFX11_NUM_GFX_RINGS; Reviewed-by: Timur Krist=C3=B3f Could you maybe move this code to a small helper function, eg. we could cal= l=20 it gfx_v11_0_calc_num_pipes_per_me() and call that from both places. Thanks & best regards, Timur > adev->gfx.num_compute_rings =3D=20 min(amdgpu_gfx_get_num_kcq(adev), > =20 AMDGPU_MAX_COMPUTE_RINGS); > } > @@ -5393,13 +5406,12 @@ static int gfx_v11_0_early_init(struct > amdgpu_ip_block *ip_block) gfx_v11_0_set_gds_init(adev); > gfx_v11_0_set_rlc_funcs(adev); > gfx_v11_0_set_mqd_funcs(adev); > - gfx_v11_0_set_imu_funcs(adev); >=20 > gfx_v11_0_init_rlcg_reg_access_ctrl(adev); >=20 > amdgpu_init_rlc_reg_funcs(adev); >=20 > - return gfx_v11_0_init_microcode(adev); > + return 0; > } >=20 > static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)