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[84.1.223.194]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a7748f32dsm20777495e9.2.2026.04.28.03.29.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 03:29:39 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org Cc: Alex Deucher , Alex Deucher Subject: Re: [PATCH 2/2] drm/radeon: add missing revision check for CI Date: Tue, 28 Apr 2026 12:29:39 +0200 Message-ID: <2010090.7Z3S40VBb9@timur-hyperion> In-Reply-To: <20260427173103.1020723-2-alexander.deucher@amd.com> References: <20260427173103.1020723-1-alexander.deucher@amd.com> <20260427173103.1020723-2-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Monday, April 27, 2026 7:31:03=E2=80=AFPM Central European Summer Time A= lex Deucher=20 wrote: > The memory level workarounds only apply to revision 0 SKUs. >=20 > Signed-off-by: Alex Deucher It is important that stable kernels (and stable distros) pick up this patch= =2E=20 Can you please add a few tags to this commit to give extra context? Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816 =46ixes: 127e056e2a82 ("drm/radeon: fix mclk vddc configuration for cards f= or=20 hawaii") =46ixes: 21b8a369046f ("drm/radeon: fix dram timing for certain hawaii boar= ds") =46ixes: 90b2fee35cb9 ("drm/radeon: fix dpm mc init for certain hawaii boar= ds") With that, this patch is also: Reviewed-by: Timur Krist=C3=B3f Thanks & best regards, Timur > --- > drivers/gpu/drm/radeon/ci_dpm.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/gpu/drm/radeon/ci_dpm.c > b/drivers/gpu/drm/radeon/ci_dpm.c index ba8db1d07c070..b47b91272b244 1006= 44 > --- a/drivers/gpu/drm/radeon/ci_dpm.c > +++ b/drivers/gpu/drm/radeon/ci_dpm.c > @@ -2461,7 +2461,8 @@ static void ci_register_patching_mc_arb(struct > radeon_device *rdev, >=20 > if (patch && > ((rdev->pdev->device =3D=3D 0x67B0) || > - (rdev->pdev->device =3D=3D 0x67B1))) { > + (rdev->pdev->device =3D=3D 0x67B1)) && > + (rdev->pdev->revision =3D=3D 0)) { > if ((memory_clock > 100000) && (memory_clock <=3D=20 125000)) { > tmp2 =3D (((0x31 * engine_clock) / 125000) -=20 1) & 0xff; > *dram_timimg2 &=3D ~0x00ff0000; > @@ -3304,7 +3305,8 @@ static int ci_populate_all_memory_levels(struct > radeon_device *rdev) pi->smc_state_table.MemoryLevel[0].EnabledForActivity > =3D 1; >=20 > if ((dpm_table->mclk_table.count >=3D 2) && > - ((rdev->pdev->device =3D=3D 0x67B0) || (rdev->pdev->device =3D=3D=20 0x67B1))) { > + ((rdev->pdev->device =3D=3D 0x67B0) || (rdev->pdev->device =3D=3D=20 0x67B1)) && > + (rdev->pdev->revision =3D=3D 0)) { > pi->smc_state_table.MemoryLevel[1].MinVddc =3D > pi->smc_state_table.MemoryLevel[0].MinVddc; > pi->smc_state_table.MemoryLevel[1].MinVddcPhases =3D > @@ -4493,7 +4495,8 @@ static int ci_register_patching_mc_seq(struct > radeon_device *rdev, >=20 > if (patch && > ((rdev->pdev->device =3D=3D 0x67B0) || > - (rdev->pdev->device =3D=3D 0x67B1))) { > + (rdev->pdev->device =3D=3D 0x67B1)) && > + (rdev->pdev->revision =3D=3D 0)) { > for (i =3D 0; i < table->last; i++) { > if (table->last >=3D=20 SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) > return -EINVAL;