From mboxrd@z Thu Jan 1 00:00:00 1970 From: Huang Rui Subject: Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state Date: Fri, 6 Jan 2017 14:19:57 +0800 Message-ID: <20170106061956.GA31759@hr-amur2> References: <1483624193-20897-1-git-send-email-ray.huang@amd.com> <1483624193-20897-3-git-send-email-ray.huang@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Felix Kuehling Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org T24gVGh1LCBKYW4gMDUsIDIwMTcgYXQgMTE6MzM6MzhBTSAtMDUwMCwgRmVsaXggS3VlaGxpbmcg d3JvdGU6Cj4gVGhpcyBjb3VsZCBiZSBkb25lIHdpdGggbXVjaCBsZXNzIGNvZGUgZHVwbGljYXRp b246Cj4gCj4gCXN0YXRpYyBjb25zdCBzdHJ1Y3Qgewo+IAkJdTMyIGZsYWc7Cj4gCQljb25zdCBj aGFyICpuYW1lOwo+IAl9IGNsb2Nrc1tdID0gewo+IAkJe0FNRF9DR19TVVBQT1JUX0dGWF9NR0NH LCAiTWVkaXVtIEdyYWluIENsb2NrIEdhdGluZyJ9LAo+IAkJe0FNRF9DR19TVVBQT1JUX0dGWF9N R0xTLCAiTWVkaXVtIEdyYWluIG1lbW9yeSBMaWdodCBTbGVlcCJ9LAo+IAkJLi4uCj4gCQl7MCwg TlVMTH0KPiAJfTsKPiAKPiAJZm9yIChpID0gMDsgY2xvY2tzW2ldLmZsYWc7IGkrKykKPiAJCXNl cV9wcmludGYobSwgIlx0JXM6ICVzXG4iLAo+IAkJCWNsb2Nrc1tpXS5uYW1lLAo+IAkJCShmbGFn cyAmIGNsb2Nrc1tpXS5mbGFnKSA/ICJPbiIgOiAiT2ZmIik7Cj4gCgpMb29rcyBiZXR0ZXIuIFRo YW5rIHlvdS4KClRoYW5rcywKUnVpCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fCmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vYW1k LWdmeAo=