From mboxrd@z Thu Jan 1 00:00:00 1970 From: Huang Rui Subject: Re: [PART1 PATCH 2/8] drm/amdgpu: add parse clock gating state Date: Fri, 6 Jan 2017 14:21:26 +0800 Message-ID: <20170106062125.GB31759@hr-amur2> References: <1483624193-20897-1-git-send-email-ray.huang@amd.com> <1483624193-20897-3-git-send-email-ray.huang@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: William Lewis Cc: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" T24gVGh1LCBKYW4gMDUsIDIwMTcgYXQgMDQ6MzQ6NDVQTSArMDAwMCwgV2lsbGlhbSBMZXdpcyB3 cm90ZToKPiBNaW5vciBuaXQuCj4gCj4gcy9HcmFpbi9HcmFpbmVkLwo+IAo+IEFsc28sIGFtZGdw dV9jbG9ja2dhdGluZ19zdGF0ZSBhcyBhIGZ1bmN0aW9uIG5hbWUgZG9lcyBub3Qgc2VlbSBleHBs aWNpdCAKPiBlbm91Z2ggYXMgdG8gd2hhdCBpdCdzIGRvaW5nLCBtYXliZSBhbWRncHVfZ2V0X2Ns b2NrZ2F0aW5nX3N0YXRlPwo+IAoKWWVwLCB0aGFua3MgdG8gcmVtaW5kZXIuCgpUaGFua3MsClJ1 aQpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwphbWQtZ2Z4 IG1haWxpbmcgbGlzdAphbWQtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3Rz LmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2FtZC1nZngK