From: "Nils Wallménius" <nils.wallmenius-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: "Nils Wallménius"
<nils.wallmenius-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: [PATCH] drm/amdgpu: simplify allocation of scratch regs
Date: Mon, 16 Jan 2017 21:56:48 +0100 [thread overview]
Message-ID: <20170116205648.2570-1-nils.wallmenius@gmail.com> (raw)
The scratch regs are sequential so there's no need to keep
them in an array, we can just return the index of the first
free register + the base register. Also change the array
of bools for keeping track of the free regs to a bitfield.
Signed-off-by: Nils Wallménius <nils.wallmenius@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 21 +++++++--------------
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 7 +------
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 7 +------
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +------
5 files changed, 11 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ffeda245..9531480 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -794,8 +794,7 @@ struct amdgpu_kiq {
struct amdgpu_scratch {
unsigned num_reg;
uint32_t reg_base;
- bool free[32];
- uint32_t reg[32];
+ uint32_t free_mask;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 01a42b6..1994335 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -42,12 +42,12 @@ int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
{
int i;
- for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
- if (adev->gfx.scratch.free[i]) {
- adev->gfx.scratch.free[i] = false;
- *reg = adev->gfx.scratch.reg[i];
- return 0;
- }
+ i = ffs(adev->gfx.scratch.free_mask);
+ if (i != 0 && i <= adev->gfx.scratch.num_reg) {
+ i--;
+ adev->gfx.scratch.free_mask &= ~(1u << i);
+ *reg = adev->gfx.scratch.reg_base + i;
+ return 0;
}
return -EINVAL;
}
@@ -62,14 +62,7 @@ int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg)
*/
void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
{
- int i;
-
- for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
- if (adev->gfx.scratch.reg[i] == reg) {
- adev->gfx.scratch.free[i] = true;
- return;
- }
- }
+ adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index b323f5e..e013243 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1794,14 +1794,9 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
{
- int i;
-
adev->gfx.scratch.num_reg = 7;
adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
- for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
- adev->gfx.scratch.free[i] = true;
- adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
- }
+ adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
}
static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index c4e1401..cfed6db 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2003,14 +2003,9 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
*/
static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
{
- int i;
-
adev->gfx.scratch.num_reg = 7;
adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
- for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
- adev->gfx.scratch.free[i] = true;
- adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
- }
+ adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c8c45ba..69543d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -749,14 +749,9 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
{
- int i;
-
adev->gfx.scratch.num_reg = 7;
adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
- for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
- adev->gfx.scratch.free[i] = true;
- adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
- }
+ adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
}
static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
--
2.10.2
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next reply other threads:[~2017-01-16 20:56 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-16 20:56 Nils Wallménius [this message]
[not found] ` <20170116205648.2570-1-nils.wallmenius-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-01-17 10:18 ` [PATCH] drm/amdgpu: simplify allocation of scratch regs Christian König
[not found] ` <c3b5469d-be9d-f4a3-d158-8335b9a0f63a-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-01-17 19:50 ` Alex Deucher
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