From: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
To: "Kuehling, Felix" <Felix.Kuehling-5C7GfCeVMHo@public.gmane.org>
Cc: "Deucher,
Alexander" <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>,
"amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] drm/amdgpu: use queue 0 for kiq ring
Date: Tue, 23 Jan 2018 09:11:06 +0800 [thread overview]
Message-ID: <20180123011105.GA2062@hr-amur2> (raw)
In-Reply-To: <ef29adff-9d94-9381-71ea-fcbda0ec48b5-5C7GfCeVMHo@public.gmane.org>
On Tue, Jan 23, 2018 at 06:28:52AM +0800, Kuehling, Felix wrote:
> KFD currently hard-codes MEC2, Pipe0, Queue0 for the HIQ. (For some
> reason KFD numbers MECs starting from 1, not 0.)
>
> So that narrows your choice for KIQ on MEC2 down to pipe == 1, queue == 0.
>
Yes, actually, we use mec2 pipe1 queue0 for KIQ at current for this patch.
Thanks
Ray
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prev parent reply other threads:[~2018-01-23 1:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-22 13:45 [PATCH] drm/amdgpu: use queue 0 for kiq ring Huang Rui
[not found] ` <1516628738-16083-1-git-send-email-ray.huang-5C7GfCeVMHo@public.gmane.org>
2018-01-22 15:19 ` Alex Deucher
2018-01-22 17:53 ` Andres Rodriguez
[not found] ` <aaf8651b-6165-19b5-5508-4f3cba3f1e85-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-01-22 20:49 ` Alex Deucher
2018-01-22 22:28 ` Felix Kuehling
[not found] ` <ef29adff-9d94-9381-71ea-fcbda0ec48b5-5C7GfCeVMHo@public.gmane.org>
2018-01-23 1:11 ` Huang Rui [this message]
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