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From: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>
To: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH] drm/amd/pp: Move common code to smu_help.c
Date: Fri, 13 Apr 2018 15:58:13 +0800	[thread overview]
Message-ID: <20180413075811.GA10330@hr-amur2> (raw)
In-Reply-To: <1523599695-23670-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>

On Fri, Apr 13, 2018 at 02:08:15PM +0800, Rex Zhu wrote:
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c   | 56 ++++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h   | 21 ++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 43 +----------------
>  3 files changed, 78 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> index e6178b0..7c23741 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
> @@ -650,3 +650,59 @@ int smu_get_voltage_dependency_table_ppt_v1(
>  
>  	return 0;
>  }
> +
> +int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> +		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> +{
> +	uint32_t i;
> +	struct watermarks *table = wt_table;
> +
> +	if (!table || wm_with_clock_ranges)
> +		return -EINVAL;
> +
> +	if (wm_with_clock_ranges->num_wm_sets_dmif > 4 || wm_with_clock_ranges->num_wm_sets_mcif > 4)
> +		return -EINVAL;
> +
> +	for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
> +		table->WatermarkRow[1][i].MinClock =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
> +			100);
> +		table->WatermarkRow[1][i].MaxClock =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
> +			100);
> +		table->WatermarkRow[1][i].MinUclk =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
> +			100);
> +		table->WatermarkRow[1][i].MaxUclk =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
> +			100);
> +		table->WatermarkRow[1][i].WmSetting = (uint8_t)
> +				wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
> +	}
> +
> +	for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
> +		table->WatermarkRow[0][i].MinClock =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
> +			100);
> +		table->WatermarkRow[0][i].MaxClock =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
> +			100);
> +		table->WatermarkRow[0][i].MinUclk =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
> +			100);
> +		table->WatermarkRow[0][i].MaxUclk =
> +			cpu_to_le16((uint16_t)
> +			(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
> +			100);
> +		table->WatermarkRow[0][i].WmSetting = (uint8_t)
> +				wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
> +	}
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> index 2243e29..916cc01 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h
> @@ -26,10 +26,27 @@
>  struct pp_atomctrl_voltage_table;
>  struct pp_hwmgr;
>  struct phm_ppt_v1_voltage_lookup_table;
> +struct Watermarks_t;
> +struct pp_wm_sets_with_clock_ranges_soc15;
>  
>  uint8_t convert_to_vid(uint16_t vddc);
>  uint16_t convert_to_vddc(uint8_t vid);
>  
> +struct watermark_row_generic_t {
> +	uint16_t MinClock;
> +	uint16_t MaxClock;
> +	uint16_t MinUclk;
> +	uint16_t MaxUclk;
> +
> +	uint8_t  WmSetting;
> +	uint8_t  Padding[3];
> +};
> +
> +struct watermarks {
> +	struct watermark_row_generic_t WatermarkRow[2][4];
> +	uint32_t     padding[7];
> +};
> +
>  extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
>  					uint32_t index,
>  					uint32_t value, uint32_t mask);
> @@ -88,6 +105,10 @@ void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
>  int smu_get_voltage_dependency_table_ppt_v1(
>  	const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
>  		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
> +
> +int smu_set_watermarks_for_clocks_ranges(void *wt_table,
> +		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> +
>  #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
>  #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
>  
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 431a0cc..7903a47 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4181,50 +4181,9 @@ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
>  	struct vega10_hwmgr *data = hwmgr->backend;
>  	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
>  	int result = 0;
> -	uint32_t i;
>  
>  	if (!data->registry_data.disable_water_mark) {
> -		for (i = 0; i < wm_with_clock_ranges->num_wm_sets_dmif; i++) {
> -			table->WatermarkRow[WM_DCEFCLK][i].MinClock =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_dcefclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_dcefclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_dmif[i].wm_min_memclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_dmif[i].wm_max_memclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_DCEFCLK][i].WmSetting = (uint8_t)
> -					wm_with_clock_ranges->wm_sets_dmif[i].wm_set_id;
> -		}
> -
> -		for (i = 0; i < wm_with_clock_ranges->num_wm_sets_mcif; i++) {
> -			table->WatermarkRow[WM_SOCCLK][i].MinClock =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_socclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_socclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_SOCCLK][i].MinUclk =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_mcif[i].wm_min_memclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
> -				cpu_to_le16((uint16_t)
> -				(wm_with_clock_ranges->wm_sets_mcif[i].wm_max_memclk_in_khz) /
> -				100);
> -			table->WatermarkRow[WM_SOCCLK][i].WmSetting = (uint8_t)
> -					wm_with_clock_ranges->wm_sets_mcif[i].wm_set_id;
> -		}
> +		smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
>  		data->water_marks_bitmap = WaterMarksExist;
>  	}
>  
> -- 
> 1.9.1
> 
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      parent reply	other threads:[~2018-04-13  7:58 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-13  6:08 [PATCH] drm/amd/pp: Move common code to smu_help.c Rex Zhu
     [not found] ` <1523599695-23670-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-04-13  7:58   ` Huang Rui [this message]

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