[bug report] drm/amd/pp: Use gfx rlc funcs directly in powerplay

From: Dan Carpenter <dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
To: Rex.Zhu-5C7GfCeVMHo@public.gmane.org
Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [bug report] drm/amd/pp: Use gfx rlc funcs directly in powerplay
Date: Thu, 17 May 2018 17:00:43 +0300	[thread overview]
Message-ID: <20180517140043.GA19537@mwanda> (raw)

Hello Rex Zhu,

The patch 62fd51275e4d: "drm/amd/pp: Use gfx rlc funcs directly in
powerplay" from Mar 23, 2018, leads to the following static checker
warning:

drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_powertune.c:977 smu7_enable_didt_config()
warn: inconsistent returns 'mutex:&adev->grbm_idx_mutex'.
  Locked on:   line 939
               line 941
               line 944
               line 949
               line 952
               line 954
               line 957
               line 959
               line 965
               line 970
  Unlocked on: line 977

drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/smu7_powertune.c
   913  int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
   914  {
   915          int result;
   916          uint32_t num_se = 0;
   917          uint32_t count, value, value2;
   918          struct amdgpu_device *adev = hwmgr->adev;
   919  
   920          num_se = adev->gfx.config.max_shader_engines;
   921  
   922          if (PP_CAP(PHM_PlatformCaps_SQRamping) ||
   923              PP_CAP(PHM_PlatformCaps_DBRamping) ||
   924              PP_CAP(PHM_PlatformCaps_TDRamping) ||
   925              PP_CAP(PHM_PlatformCaps_TCPRamping)) {
   926  
   927                  adev->gfx.rlc.funcs->enter_safe_mode(adev);
   928                  mutex_lock(&adev->grbm_idx_mutex);
                        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

   929                  value = 0;
   930                  value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
   931                  for (count = 0; count < num_se; count++) {
   932                          value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK
   933                                  | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK
   934                                  | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT);
   935                          cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
   936  
   937                          if (hwmgr->chip_id == CHIP_POLARIS10) {
   938                                  result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
   939                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
                                                                                                  ^^^^^^^^^^^^^
etc...

   940                                  result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
   941                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   942                          } else if (hwmgr->chip_id == CHIP_POLARIS11) {
   943                                  result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
   944                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   945                                  if (hwmgr->is_kicker)
   946                                          result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
   947                                  else
   948                                          result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
   949                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   950                          } else if (hwmgr->chip_id == CHIP_POLARIS12) {
   951                                  result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
   952                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   953                                  result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12);
   954                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   955                          } else if (hwmgr->chip_id == CHIP_VEGAM) {
   956                                  result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM);
   957                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   958                                  result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM);
   959                                  PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", return result);
   960                          }
   961                  }
   962                  cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
   963  
   964                  result = smu7_enable_didt(hwmgr, true);
   965                  PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", return result);
   966  
   967                  if (hwmgr->chip_id == CHIP_POLARIS11) {
   968                          result = smum_send_msg_to_smc(hwmgr,
   969                                                  (uint16_t)(PPSMC_MSG_EnableDpmDidt));
   970                          PP_ASSERT_WITH_CODE((0 == result),
   971                                          "Failed to enable DPM DIDT.", return result);
   972                  }
   973                  mutex_unlock(&adev->grbm_idx_mutex);
   974                  adev->gfx.rlc.funcs->exit_safe_mode(adev);
   975          }
   976  
   977          return 0;
   978  }

regards,
dan carpenter
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