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From: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 1/2] drm/amd/powerpaly: force to update all clock tables on OD reset
Date: Wed, 8 May 2019 14:43:32 +0800	[thread overview]
Message-ID: <20190508064333.16154-1-evan.quan@amd.com> (raw)

On OD reset, the clock tables in SMU need to be reset to default.

Change-Id: Ibefc6636a436404839d9db6fb52e738f102c413f
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 346cf61d55f6..b298aba1206b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -5176,6 +5176,10 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 		memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
 		vega10_odn_initial_default_setting(hwmgr);
 		vega10_odn_update_power_state(hwmgr);
+		/* force to update all clock tables */
+		data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
+					      DPMTABLE_UPDATE_MCLK |
+					      DPMTABLE_UPDATE_SOCCLK;
 		return 0;
 	} else if (PP_OD_COMMIT_DPM_TABLE == type) {
 		vega10_check_dpm_table_updated(hwmgr);
-- 
2.21.0

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             reply	other threads:[~2019-05-08  6:43 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-08  6:43 Evan Quan [this message]
     [not found] ` <20190508064333.16154-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-05-08  6:43   ` [PATCH 2/2] drm/amd/powerplay: update Vega10 ACG Avfs Gb parameters Evan Quan
     [not found]     ` <20190508064333.16154-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-05-09  5:36       ` Alex Deucher

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