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From: David Francis <David.Francis@amd.com>
To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org
Cc: David Francis <David.Francis@amd.com>
Subject: [PATCH v2 03/14] Revert "drm/amd/display: add global master update lock for DCN2"
Date: Tue, 20 Aug 2019 15:11:52 -0400	[thread overview]
Message-ID: <20190820191203.25807-4-David.Francis@amd.com> (raw)
In-Reply-To: <20190820191203.25807-1-David.Francis@amd.com>

This reverts commit 55a6f5bbcf00a49565946c0a9b8c716313dc6c05.

This commit was accidentally promoted twice

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  4 --
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 63 +------------------
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |  3 -
 .../amd/display/dc/inc/hw/timing_generator.h  |  2 -
 4 files changed, 1 insertion(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fa8a73f6c8e3..e146d1d8d45e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -575,10 +575,6 @@ enum dc_status dcn20_enable_stream_timing(
 			pipe_ctx->stream->signal,
 			true);
 
-	if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
-		pipe_ctx->stream_res.tg->funcs->setup_global_lock(
-				pipe_ctx->stream_res.tg);
-
 	if (odm_pipe)
 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 				odm_pipe->stream_res.opp,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 99070e93020b..2137e2be2140 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -333,65 +333,6 @@ void optc2_triplebuffer_unlock(struct timing_generator *optc)
 
 }
 
-
-void optc2_setup_global_lock(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-	uint32_t v_blank_start = 0;
-	uint32_t h_blank_start = 0, h_total = 0;
-
-	REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
-
-	REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
-
-	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
-
-	REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
-
-	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
-	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
-			MASTER_UPDATE_LOCK_DB_X,
-			h_blank_start - 200 - 1,
-			MASTER_UPDATE_LOCK_DB_Y,
-			v_blank_start - 1);
-}
-
-void optc2_lock_global(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-			OTG_MASTER_UPDATE_LOCK, 1);
-
-	/* Should be fast, status does not update on maximus */
-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-				UPDATE_LOCK_STATUS, 1,
-				1, 10);
-}
-
-void optc2_lock(struct timing_generator *optc)
-{
-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
-
-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
-			OTG_MASTER_UPDATE_LOCK, 1);
-
-	/* Should be fast, status does not update on maximus */
-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
-				UPDATE_LOCK_STATUS, 1,
-				1, 10);
-}
-
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
 {
 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
@@ -486,10 +427,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
 		.triplebuffer_lock = optc2_triplebuffer_lock,
 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
 		.disable_reset_trigger = optc1_disable_reset_trigger,
-		.lock = optc2_lock,
+		.lock = optc1_lock,
 		.unlock = optc1_unlock,
-		.lock_global = optc2_lock_global,
-		.setup_global_lock = optc2_setup_global_lock,
 		.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 47cb4de1564c..32a58431fd09 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -106,9 +106,6 @@ void optc2_get_optc_source(struct timing_generator *optc,
 
 void optc2_triplebuffer_lock(struct timing_generator *optc);
 void optc2_triplebuffer_unlock(struct timing_generator *optc);
-void optc2_lock(struct timing_generator *optc);
-void optc2_lock_global(struct timing_generator *optc);
-void optc2_setup_global_lock(struct timing_generator *optc);
 void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
 void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
 void optc2_program_manual_trigger(struct timing_generator *optc);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index f607ef24c766..e0713d6d6c8d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -189,10 +189,8 @@ struct timing_generator_funcs {
 	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 	void (*setup_global_swap_lock)(struct timing_generator *tg,
 							const struct dcp_gsl_params *gsl_params);
-	void (*setup_global_lock)(struct timing_generator *tg);
 	void (*unlock)(struct timing_generator *tg);
 	void (*lock)(struct timing_generator *tg);
-	void (*lock_global)(struct timing_generator *tg);
 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
-- 
2.17.1

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  parent reply	other threads:[~2019-08-20 19:11 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-20 19:11 [PATCH v2 00/14] Display Stream Compression (DSC) for AMD Navi David Francis
2019-08-20 19:11 ` [PATCH v2 01/14] Revert "drm/amd/display: skip dsc config for navi10 bring up" David Francis
2019-08-20 19:11 ` David Francis [this message]
2019-08-20 19:11 ` [PATCH v2 04/14] Revert "drm/amd/display: Fix underscan not using proper scaling" David Francis
     [not found] ` <20190820191203.25807-1-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 19:11   ` [PATCH v2 02/14] Revert "drm/amd/display: navi10 bring up skip dsc encoder config" David Francis
2019-08-20 19:11   ` [PATCH v2 05/14] drm/amd/display: Enable SST DSC in DM David Francis
2019-08-20 19:11   ` [PATCH v2 06/14] drm/dp-mst: Use dc and drm helpers to compute timeslots David Francis
     [not found]     ` <20190820191203.25807-7-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 20:43       ` Lyude Paul
     [not found]         ` <eccdbdb90afa28079a92b9cd959a1cb54ed952b3.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2019-08-21 12:27           ` Kazlauskas, Nicholas
     [not found]             ` <f63c563e-3aa5-0772-559b-6b34ef612495-5C7GfCeVMHo@public.gmane.org>
2019-08-21 18:57               ` Lyude Paul
2019-08-20 19:11   ` [PATCH v2 07/14] drm/amd/display: Initialize DSC PPS variables to 0 David Francis
2019-08-20 19:11   ` [PATCH v2 08/14] drm/dp-mst: Parse FEC capability on MST ports David Francis
     [not found]     ` <20190820191203.25807-9-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 20:40       ` Lyude Paul
2019-08-20 19:11   ` [PATCH v2 10/14] drm/dp-mst: Fill branch->num_ports David Francis
     [not found]     ` <20190820191203.25807-11-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 21:08       ` Lyude Paul
2019-08-20 19:12   ` [PATCH v2 11/14] drm/amd/display: Validate DSC caps on MST endpoints David Francis
     [not found]     ` <20190820191203.25807-12-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 20:34       ` Lyude Paul
2019-08-21 18:14       ` Kazlauskas, Nicholas
2019-08-20 19:12   ` [PATCH v2 12/14] drm/amd/display: Write DSC enable to MST DPCD David Francis
2019-08-20 19:12   ` [PATCH v2 13/14] drm/amd/display: MST DSC compute fair share David Francis
2019-08-20 19:11 ` [PATCH v2 09/14] drm/dp-mst: Export symbols for dpcd read/write David Francis
     [not found]   ` <20190820191203.25807-10-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 21:02     ` Lyude Paul
     [not found]       ` <773c80494087854b72ffb85938f0ea54bd89c121.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2019-08-20 21:35         ` Li, Sun peng (Leo)
2019-08-20 19:12 ` [PATCH v2 14/14] drm/amd/display: Trigger modesets on MST DSC connectors David Francis
     [not found]   ` <20190820191203.25807-15-David.Francis-5C7GfCeVMHo@public.gmane.org>
2019-08-20 21:09     ` Lyude Paul
     [not found]       ` <f7272de2841c61f1297f0fce493efe5dd5317dfa.camel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2019-08-21 12:25         ` Kazlauskas, Nicholas

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