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[165.204.84.11]) by smtp.gmail.com with ESMTPSA id h16sm42164qtp.1.2020.06.01.11.03.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 11:03:10 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: amd-gfx@lists.freedesktop.org Subject: [PATCH 020/207] drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2) Date: Mon, 1 Jun 2020 13:59:32 -0400 Message-Id: <20200601180239.1267430-17-alexander.deucher@amd.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200601180239.1267430-1-alexander.deucher@amd.com> References: <20200601180239.1267430-1-alexander.deucher@amd.com> MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Likun Gao , Hawking Zhang Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Likun Gao Add irq src headers for additional SDMA blocks. v2: Add missing licenses (Alex) Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- .../include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h | 45 +++++++++++++++++++ .../include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h | 45 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h new file mode 100644 index 000000000000..daa498478ba6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma2/irqsrcs_sdma2_5_0.h @@ -0,0 +1,45 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __IRQSRCS_SDMA2_5_0_H__ +#define __IRQSRCS_SDMA2_5_0_H__ + + +#define SDMA2_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete +#define SDMA2_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout +#define SDMA2_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt +#define SDMA2_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error +#define SDMA2_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 +#define SDMA2_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2 +#define SDMA2_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1 +#define SDMA2_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap +#define SDMA2_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout) +#define SDMA2_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout +#define SDMA2_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error +#define SDMA2_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List +#define SDMA2_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole +#define SDMA2_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty +#define SDMA2_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid +#define SDMA2_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen +#define SDMA2_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout +#define SDMA2_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection + +#endif // __IRQSRCS_SDMA2_5_0_H__ diff --git a/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h b/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h new file mode 100644 index 000000000000..e0ee820d5097 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/sdma3/irqsrcs_sdma3_5_0.h @@ -0,0 +1,45 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __IRQSRCS_SDMA3_5_0_H__ +#define __IRQSRCS_SDMA3_5_0_H__ + + +#define SDMA3_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete +#define SDMA3_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout +#define SDMA3_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt +#define SDMA3_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error +#define SDMA3_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 +#define SDMA3_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2 +#define SDMA3_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1 +#define SDMA3_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap +#define SDMA3_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout) +#define SDMA3_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout +#define SDMA3_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error +#define SDMA3_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List +#define SDMA3_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole +#define SDMA3_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty +#define SDMA3_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid +#define SDMA3_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen +#define SDMA3_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout +#define SDMA3_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection + +#endif // __IRQSRCS_SDMA3_5_0_H__ -- 2.25.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx