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From: Peter Zijlstra <peterz@infradead.org>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>,
	H Peter Anvin <hpa@zytor.com>, Dave Jiang <dave.jiang@intel.com>,
	Ashok Raj <ashok.raj@intel.com>, Joerg Roedel <joro@8bytes.org>,
	x86 <x86@kernel.org>, amd-gfx <amd-gfx@lists.freedesktop.org>,
	Ingo Molnar <mingo@redhat.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Yu-cheng Yu <yu-cheng.yu@intel.com>,
	Andrew Donnellan <ajd@linux.ibm.com>,
	Borislav Petkov <bp@alien8.de>,
	Sohil Mehta <sohil.mehta@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Tony Luck <tony.luck@intel.com>,
	linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	Felix Kuehling <Felix.Kuehling@amd.com>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	iommu@lists.linux-foundation.org,
	Jacob Jun Pan <jacob.jun.pan@intel.com>,
	Frederic Barrat <fbarrat@linux.ibm.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Lu Baolu <baolu.lu@linux.intel.com>
Subject: Re: [PATCH v2 12/12] x86/traps: Fix up invalid PASID
Date: Mon, 15 Jun 2020 09:56:49 +0200	[thread overview]
Message-ID: <20200615075649.GK2497@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1592008893-9388-13-git-send-email-fenghua.yu@intel.com>

On Fri, Jun 12, 2020 at 05:41:33PM -0700, Fenghua Yu wrote:
> +/*
> + * Apply some heuristics to see if the #GP fault was caused by a thread
> + * that hasn't had the IA32_PASID MSR initialized.  If it looks like that
> + * is the problem, try initializing the IA32_PASID MSR. If the heuristic
> + * guesses incorrectly, take one more #GP fault.

How is that going to help? Aren't we then going to run this same
heuristic again and again and again?

> + */
> +bool __fixup_pasid_exception(void)
> +{
> +	u64 pasid_msr;
> +	unsigned int pasid;
> +
> +	/*
> +	 * This function is called only when this #GP was triggered from user
> +	 * space. So the mm cannot be NULL.
> +	 */
> +	pasid = current->mm->pasid;
> +	/* If the mm doesn't have a valid PASID, then can't help. */
> +	if (invalid_pasid(pasid))
> +		return false;
> +
> +	/*
> +	 * Since IRQ is disabled now, the current task still owns the FPU on

That's just weird and confusing. What you want to say is that you rely
on the exception disabling the interrupt.

> +	 * this CPU and the PASID MSR can be directly accessed.
> +	 *
> +	 * If the MSR has a valid PASID, the #GP must be for some other reason.
> +	 *
> +	 * If rdmsr() is really a performance issue, a TIF_ flag may be
> +	 * added to check if the thread has a valid PASID instead of rdmsr().

I don't understand any of this. Nobody except us writes to this MSR, we
should bloody well know what's in it. What gives?

> +	 */
> +	rdmsrl(MSR_IA32_PASID, pasid_msr);
> +	if (pasid_msr & MSR_IA32_PASID_VALID)
> +		return false;
> +
> +	/* Fix up the MSR if the MSR doesn't have a valid PASID. */
> +	wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID);
> +
> +	return true;
> +}
> -- 
> 2.19.1
> 
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  parent reply	other threads:[~2020-06-15 13:21 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-13  0:41 [PATCH v2 00/12] x86: tag application address space for devices Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 01/12] iommu: Change type of pasid to unsigned int Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 02/12] ocxl: " Fenghua Yu
2020-06-18  8:05   ` Frederic Barrat
2020-06-18 15:37     ` Fenghua Yu
2020-06-18 16:56       ` Frederic Barrat
2020-06-13  0:41 ` [PATCH v2 03/12] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 04/12] docs: x86: Add documentation for SVA (Shared Virtual Addressing) Fenghua Yu
2020-06-13 12:17   ` Lu Baolu
2020-06-15 23:16     ` Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 05/12] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 06/12] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 07/12] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 08/12] mm: Define pasid in mm Fenghua Yu
2020-06-16  8:28   ` Jean-Philippe Brucker
2020-06-16 15:11     ` Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 09/12] fork: Clear PASID for new mm Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 10/12] x86/process: Clear PASID state for a newly forked/cloned thread Fenghua Yu
2020-06-13  0:41 ` [PATCH v2 11/12] x86/mmu: Allocate/free PASID Fenghua Yu
2020-06-13 13:07   ` Lu Baolu
2020-06-15  2:13   ` Lu Baolu
2020-06-13  0:41 ` [PATCH v2 12/12] x86/traps: Fix up invalid PASID Fenghua Yu
2020-06-15  7:53   ` Peter Zijlstra
2020-06-15  7:56   ` Peter Zijlstra [this message]
2020-06-15 15:48     ` Fenghua Yu
2020-06-15 16:03       ` Peter Zijlstra
2020-06-15 17:11         ` Luck, Tony
2020-06-15 18:12         ` Fenghua Yu
2020-06-15 18:31           ` Peter Zijlstra
2020-06-15 18:55             ` Fenghua Yu
2020-06-15 19:09               ` Peter Zijlstra
2020-06-15 20:17                 ` Fenghua Yu
2020-06-15 20:51                   ` Andy Lutomirski
2020-06-15 20:56                     ` Luck, Tony
2020-06-15 21:18                       ` Andy Lutomirski
2020-06-15 21:24                         ` Luck, Tony
2020-06-15 21:53                   ` Peter Zijlstra
2020-06-16 23:23                 ` Fenghua Yu
2020-06-17  8:31                   ` Peter Zijlstra
2020-06-15 18:19         ` Raj, Ashok
2020-06-15 18:32           ` Peter Zijlstra
2020-06-15  7:52 ` [PATCH v2 00/12] x86: tag application address space for devices Peter Zijlstra
2020-06-15 14:53   ` Fenghua Yu

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