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Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXMB02.amd.com (165.204.84.17) by DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3088.18 via Frontend Transport; Mon, 15 Jun 2020 19:01:58 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB02.amd.com (10.181.40.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 15 Jun 2020 14:01:57 -0500 Received: from SATLEXMB01.amd.com (10.181.40.142) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 15 Jun 2020 14:01:57 -0500 Received: from jzuo-linux.amd.com (10.180.168.240) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Mon, 15 Jun 2020 14:01:55 -0500 From: "Jerry (Fangzhi) Zuo" To: Subject: [PATCH 2/2] drm/amd/display: Update bounding box states Date: Mon, 15 Jun 2020 15:01:35 -0400 Message-ID: <20200615190135.16562-2-Jerry.Zuo@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200615190135.16562-1-Jerry.Zuo@amd.com> References: <20200615190135.16562-1-Jerry.Zuo@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6SPR00MB245 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander.Deucher@amd.com, Jerry Zuo , harry.wentland@amd.com, Nicholas.Kazlauskas@amd.com, Alvin Lee Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [Why] We need to update each p-state in the bounding box [How] Update states when assigning values to clocks Signed-off-by: Alvin Lee Signed-off-by: Jerry (Fangzhi) Zuo Reviewed-by: Hersen Wu --- .../drm/amd/display/dc/dcn30/dcn30_resource.c | 65 +++++++------------ 1 file changed, 23 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c index 821bde9a376e..27e84d90306b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c @@ -168,17 +168,18 @@ struct _vcs_dpi_ip_params_st dcn3_0_ip = { struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { .clock_limits = { - /* State 0 should have clocks set below WM set B minimums */ { .state = 0, - }, - /* State 1 is max */ - { - .state = 1, + .dispclk_mhz = 1217.0, + .dppclk_mhz = 1217.0, + .phyclk_mhz = 810.0, + .phyclk_d18_mhz = 667.0, + .socclk_mhz = 1200.0, + .dscclk_mhz = 405.6, }, }, .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ - .num_states = 2, + .num_states = 1, .sr_exit_time_us = 12, .sr_enter_plus_exit_time_us = 20, .urgent_latency_us = 4.0, @@ -204,6 +205,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { .round_trip_ping_latency_dcfclk_cycles = 191, .urgent_out_of_order_return_per_channel_bytes = 4096, .channel_interleave_bytes = 256, + .num_banks = 8, .gpuvm_min_page_size_bytes = 4096, .hostvm_min_page_size_bytes = 4096, .dram_clock_change_latency_us = 404, @@ -2354,43 +2356,22 @@ static void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; - } - } - /* Fill all states with max values of all other clocks */ - for (i = 0; i < dcn3_0_soc.num_states; i++) { - /* Some clocks can come from bw_params, if so fill from bw_params[1], otherwise fill from dcn3_0_soc[1] */ - /* Temporarily ignore bw_params values */ - - /* DTBCLK */ - /*if (bw_params->clk_table.entries[0].dtbclk_mhz) - dcn3_0_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[1].dtbclk_mhz; - else*/ - dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[1].dtbclk_mhz; - - /* DISPCLK */ - /*if (bw_params->clk_table.entries[0].dispclk_mhz) - dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz; - else*/ - dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn3_0_soc.clock_limits[1].dispclk_mhz; - - /* DPPCLK */ - /*if (bw_params->clk_table.entries[0].dppclk_mhz) - dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz; - else*/ - dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn3_0_soc.clock_limits[1].dppclk_mhz; - - /* PHYCLK */ - /*if (bw_params->clk_table.entries[0].phyclk_mhz) - dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz; - else*/ - dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn3_0_soc.clock_limits[1].phyclk_mhz; - - /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ - /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ - dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[1].phyclk_d18_mhz; - dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[1].socclk_mhz; - dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[1].dscclk_mhz; + /* Fill all states with max values of all other clocks */ + dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; + dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; + dcn3_0_soc.clock_limits[i].dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; + dcn3_0_soc.clock_limits[i].phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; + /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ + /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ + dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; + dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; + dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; + } + /* re-init DML with updated bb */ + dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); + if (dc->current_state) + dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); } /* re-init DML with updated bb */ -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx