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Mon, 22 Jun 2020 17:05:26 -0700 (PDT) Received: from jgg by mlx with local (Exim 4.93) (envelope-from ) id 1jnWRJ-00CHPu-Cd; Mon, 22 Jun 2020 21:05:25 -0300 Date: Mon, 22 Jun 2020 21:05:25 -0300 From: Jason Gunthorpe To: Jerome Glisse Subject: Re: [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations Message-ID: <20200623000525.GX6578@ziepe.ca> References: <20200618172338.GM6578@ziepe.ca> <20200619113934.GN6578@ziepe.ca> <20200619151551.GP6578@ziepe.ca> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <20200619201011.GB13117@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200619201011.GB13117@redhat.com> X-Mailman-Approved-At: Tue, 23 Jun 2020 07:49:16 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rdma , Thomas =?utf-8?B?SGVsbHN0csO2bSAoSW50ZWwp?= , Maarten Lankhorst , LKML , DRI Development , Christian =?utf-8?B?S8O2bmln?= , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Thomas Hellstrom , amd-gfx list , Daniel Vetter , Daniel Vetter , Mika Kuoppala , Intel Graphics Development , "open list:DMA BUFFER SHARING FRAMEWORK" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Fri, Jun 19, 2020 at 04:10:11PM -0400, Jerome Glisse wrote: > Maybe we can audit how user ptr buffer are use today and see if > we can define a usage pattern that would allow to cut corner in > kernel. For instance we could use mmu notifier just to block CPU > pte update while we do GUP and thus never wait on dma fence. The DMA fence is the main problem, if you can think of a way to avoid it then it would be great! > Then GPU driver just keep the GUP pin around until they are done > with the page. They can also use the mmu notifier to keep a flag > so that the driver know if it needs to redo a GUP ie: > > The notifier path: > GPU_mmu_notifier_start_callback(range) > gpu_lock_cpu_pagetable(range) > for_each_bo_in(bo, range) { > bo->need_gup = true; > } > gpu_unlock_cpu_pagetable(range) So some kind of invalidation tracking? But this doesn't solve COW and Fork problem? > > It is kind of unrelated to HMM, it just shouldn't be using mmu > > notifiers to replace page pinning.. > > Well my POV is that if you abide by rules HMM defined then you do > not need to pin pages. The rule is asynchronous device page table > update. I think one of the hmm rules is to not block notifiers for a long time, which these scheme seem to violate already. Pinning for a long time is less bad than blocing notifiers for a long time, IMHO Jason _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx