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From: Evan Quan <evan.quan@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com, Evan Quan <evan.quan@amd.com>
Subject: [PATCH 5/6] drm/amd/powerplay: maximum the code sharing on thermal irq setting
Date: Fri,  3 Jul 2020 16:58:17 +0800	[thread overview]
Message-ID: <20200703085818.7800-5-evan.quan@amd.com> (raw)
In-Reply-To: <20200703085818.7800-1-evan.quan@amd.com>

Put the common code in smu_v11_0.c instead of having one copy each.

Change-Id: I6d0c27c5810ebc3273ef8b4fae07ac6dbed2715c
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3404db490eb3..86a118a3a80c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1089,10 +1089,6 @@ int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
 	struct amdgpu_device *adev = smu->adev;
 
 	if (smu->smu_table.thermal_controller_type) {
-		ret = smu_set_thermal_range(smu, smu->thermal_range);
-		if (ret)
-			return ret;
-
 		ret = amdgpu_irq_get(adev, &smu->irq_source, 0);
 		if (ret)
 			return ret;
@@ -1347,6 +1343,8 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
 				   unsigned tyep,
 				   enum amdgpu_interrupt_state state)
 {
+	struct smu_context *smu = &adev->smu;
+	uint32_t low, high;
 	uint32_t val = 0;
 
 	switch (state) {
@@ -1367,9 +1365,19 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
 		break;
 	case AMDGPU_IRQ_STATE_ENABLE:
 		/* For THM irqs */
+		low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+				smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+		high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+				smu->thermal_range.software_shutdown_temp);
+
 		val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
+		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
 		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
+		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
+		val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
+		val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 		WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
 
 		val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
-- 
2.27.0

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  parent reply	other threads:[~2020-07-03  8:59 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-03  8:58 [PATCH 1/6] drm/amd/powerplay: correct Navi1X temperature limit settings Evan Quan
2020-07-03  8:58 ` [PATCH 2/6] drm/amd/powerplay: correct Sienna Cichlid " Evan Quan
2020-07-03  8:58 ` [PATCH 3/6] drm/amd/powerplay: cache the software_shutdown_temp Evan Quan
2020-07-03  8:58 ` [PATCH 4/6] drm/amd/powerplay: sort the call flow on temperature ranges retrieving Evan Quan
2020-07-03  8:58 ` Evan Quan [this message]
2020-07-03  8:58 ` [PATCH 6/6] drm/amd/powerplay: drop unused code around thermal range setting Evan Quan
2020-07-09 20:54   ` Alex Deucher

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