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[165.204.84.11]) by smtp.gmail.com with ESMTPSA id m67sm2301237qkf.98.2020.09.25.13.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2020 13:11:13 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: amd-gfx@lists.freedesktop.org Subject: [PATCH 14/45] drm/amdgpu: add gmc v10 supports for van gogh (v3) Date: Fri, 25 Sep 2020 16:09:58 -0400 Message-Id: <20200925201029.1738724-14-alexander.deucher@amd.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20200925201029.1738724-1-alexander.deucher@amd.com> References: <20200925201029.1738724-1-alexander.deucher@amd.com> MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Huang Rui Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Huang Rui Add gfx memory controller support for van gogh. v2: don't use dynamic invalidate eng allocation for van gogh. v3: squash in other fixes Signed-off-by: Huang Rui Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 33 ++++++++++++++++++++------ 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 31359e519d69..fa0a0c8a6b11 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -677,7 +677,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, u64 base = 0; if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) base = gfxhub_v2_1_get_fb_location(adev); else base = gfxhub_v2_0_get_fb_location(adev); @@ -690,7 +691,8 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, /* base offset of vram pages */ if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev); else adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev); @@ -726,6 +728,13 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); +#ifdef CONFIG_X86_64 + if (adev->flags & AMD_IS_APU) { + adev->gmc.aper_base = gfxhub_v2_1_get_mc_fb_offset(adev); + adev->gmc.aper_size = adev->gmc.real_vram_size; + } +#endif + /* In case the PCI BAR is larger than the actual amount of vram */ adev->gmc.visible_vram_size = adev->gmc.aper_size; if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) @@ -739,6 +748,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_VANGOGH: default: adev->gmc.gart_size = 512ULL << 20; break; @@ -778,7 +788,8 @@ static int gmc_v10_0_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) gfxhub_v2_1_init(adev); else gfxhub_v2_0_init(adev); @@ -787,7 +798,10 @@ static int gmc_v10_0_sw_init(void *handle) spin_lock_init(&adev->gmc.invalidate_lock); - if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) { + if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; + adev->gmc.vram_width = 64; + } else if (amdgpu_emu_mode == 1) { adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ } else { @@ -805,6 +819,7 @@ static int gmc_v10_0_sw_init(void *handle) case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_VANGOGH: adev->num_vmhubs = 2; /* * To fulfill 4-level page support, @@ -918,6 +933,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: + case CHIP_VANGOGH: break; default: break; @@ -945,7 +961,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) return r; if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) r = gfxhub_v2_1_gart_enable(adev); else r = gfxhub_v2_0_gart_enable(adev); @@ -970,7 +987,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) false : true; if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) gfxhub_v2_1_set_fault_enable_default(adev, value); else gfxhub_v2_0_set_fault_enable_default(adev, value); @@ -1015,7 +1033,8 @@ static int gmc_v10_0_hw_init(void *handle) static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) { if (adev->asic_type == CHIP_SIENNA_CICHLID || - adev->asic_type == CHIP_NAVY_FLOUNDER) + adev->asic_type == CHIP_NAVY_FLOUNDER || + adev->asic_type == CHIP_VANGOGH) gfxhub_v2_1_gart_disable(adev); else gfxhub_v2_0_gart_disable(adev); -- 2.25.4 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx