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From: Jinzhou Su <Jinzhou.Su@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Jinzhou Su <Jinzhou.Su@amd.com>,
	prakash.kamliya@amd.com, ray.huang@amd.com
Subject: [PATCH] drm/amdgpu: Set doorbell range for gfx ring
Date: Fri, 27 Nov 2020 16:09:07 +0800	[thread overview]
Message-ID: <20201127080907.12337-1-Jinzhou.Su@amd.com> (raw)

If there are 2 gfx rings, the doorbell lower range of second ring
will override the first ring.

Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ffbda6680a68..f33e54b01d3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -6357,8 +6357,11 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
 				    DOORBELL_EN, 0);
 	mqd->cp_rb_doorbell_control = tmp;
 
-	/* set doorbell range */
-	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
+	/*if there are 2 gfx rings, set the lower doorbell range of the first ring,
+	 *otherwise the range of the second ring will override the first ring */
+	if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
+		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
+
 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
 	ring->wptr = 0;
 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
-- 
2.17.1

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             reply	other threads:[~2020-11-27  8:09 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-27  8:09 Jinzhou Su [this message]
2020-11-27  8:42 ` [PATCH] drm/amdgpu: Set doorbell range for gfx ring Huang Rui

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