From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Sasha Levin <sashal@kernel.org>, Sung Lee <sung.lee@amd.com>,
amd-gfx@lists.freedesktop.org,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
dri-devel@lists.freedesktop.org,
Alex Deucher <alexander.deucher@amd.com>,
Tony Cheng <Tony.Cheng@amd.com>
Subject: [PATCH AUTOSEL 5.4 080/130] drm/amd/display: Update dram_clock_change_latency for DCN2.1
Date: Tue, 22 Dec 2020 21:17:23 -0500 [thread overview]
Message-ID: <20201223021813.2791612-80-sashal@kernel.org> (raw)
In-Reply-To: <20201223021813.2791612-1-sashal@kernel.org>
From: Sung Lee <sung.lee@amd.com>
[ Upstream commit 901c1ec05ef277ce9d43cb806a225b28b3efe89a ]
[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.
[HOW]
Update latency from 23.84 to 11.72.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index bb7add5ea2273..a6d5beada6634 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -257,7 +257,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.num_banks = 8,
.num_chans = 4,
.vmm_page_size_bytes = 4096,
- .dram_clock_change_latency_us = 23.84,
+ .dram_clock_change_latency_us = 11.72,
.return_bus_width_bytes = 64,
.dispclk_dppclk_vco_speed_mhz = 3600,
.xfc_bus_transport_time_us = 4,
--
2.27.0
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next prev parent reply other threads:[~2020-12-23 2:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20201223021813.2791612-1-sashal@kernel.org>
2020-12-23 2:16 ` [PATCH AUTOSEL 5.4 006/130] drm/amd/display: Do not silently accept DCC for multiplane formats Sasha Levin
2020-12-29 14:54 ` Deucher, Alexander
2021-01-04 21:20 ` Kazlauskas, Nicholas
2020-12-23 2:16 ` [PATCH AUTOSEL 5.4 032/130] drm/amd/amdgpu: Add rev_id workaround logic for SRIOV setup Sasha Levin
2020-12-23 2:17 ` Sasha Levin [this message]
2020-12-23 2:17 ` [PATCH AUTOSEL 5.4 096/130] drm/amd/display: Revert DCN2.1 dram_clock_change_latency update Sasha Levin
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