From: Victor Zhao <Victor.Zhao@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Victor Zhao <Victor.Zhao@amd.com>
Subject: [PATCH] drm/amdgpu/psp: fix psp gfx ctrl cmds
Date: Tue, 5 Jan 2021 15:08:22 +0800 [thread overview]
Message-ID: <20210105070822.25795-1-Victor.Zhao@amd.com> (raw)
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux,
according to psp, linux cmds are not correct
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 26 +++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index d65a5339d354..602ea5cd9f3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -39,18 +39,20 @@
*/
enum psp_gfx_crtl_cmd_id
{
- GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
- GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
- GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
- GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
- GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
- GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
- GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
- GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
- GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */
- GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
-
- GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
+ GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
+ GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
+ GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
+ GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
+ GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
+ GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
+ GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
+ GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
+ GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to PSP for SRIOV ring write pointer update */
+ GFX_CTRL_CMD_ID_MODE2_RST = 0x000A0000, /* trigger the Mode 2 reset */
+ GFX_CTRL_CMD_ID_DESTROY_RBI_RING = 0x000B0000, /* destroy RBI ring */
+ GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
+
+ GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
};
--
2.25.1
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next reply other threads:[~2021-01-05 7:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 7:08 Victor Zhao [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-01-05 3:13 [PATCH] drm/amdgpu/psp: fix psp gfx ctrl cmds Victor
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