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From: Darren Powell <darren.powell@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Darren Powell <darren.powell@amd.com>
Subject: [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
Date: Thu, 22 Apr 2021 23:22:35 -0400	[thread overview]
Message-ID: <20210423032236.6379-3-darren.powell@amd.com> (raw)
In-Reply-To: <20210423032236.6379-1-darren.powell@amd.com>

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch ignores a .force_clk_levels(SMU_DCEFCLK) call and issues an
info message.

Signed-off-by: Darren Powell <darren.powell@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c         | 5 ++++-
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f827096dc849..ac13042672ea 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1443,7 +1443,6 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1463,6 +1462,10 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			return size;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
+
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 72d9c1be1835..d2fd44b903ca 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1127,7 +1127,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 	case SMU_SOCCLK:
 	case SMU_MCLK:
 	case SMU_UCLK:
-	case SMU_DCEFCLK:
 	case SMU_FCLK:
 		/* There is only 2 levels for fine grained DPM */
 		if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1147,6 +1146,9 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
 		if (ret)
 			goto forec_level_out;
 		break;
+	case SMU_DCEFCLK:
+		dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+		break;
 	default:
 		break;
 	}
-- 
2.25.1

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  parent reply	other threads:[~2021-04-23  3:23 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-23  3:22 [PATCH v2 0/3] Prevent set of DCEFCLK on smu_v11 gpus Darren Powell
2021-04-23  3:22 ` [PATCH 1/3] amdgpu/pm: add extra info to SMU msg pre-check failed message Darren Powell
2021-04-23  3:22 ` Darren Powell [this message]
2021-04-23  3:22 ` [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and newer gpus Darren Powell
2021-04-23  5:24 ` [PATCH v2 0/3] Prevent set of DCEFCLK on smu_v11 gpus Feng, Kenneth
  -- strict thread matches above, loose matches on Subject: below --
2021-04-16 22:29 [PATCH " Darren Powell
2021-04-16 22:29 ` [PATCH 2/3] amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID Darren Powell

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