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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Wyatt Wood [Why] Need to get current DMUB time. [How] Add get_current_time interface to dmub_srv. Signed-off-by: Wyatt Wood Reviewed-by: Aric Cyr Acked-by: Stylon Wang --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++--------- .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 8 ++-- drivers/gpu/drm/amd/display/dc/dm_services.h | 1 - drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 5 +++ .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 5 ++- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 1 + 7 files changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d6f11dbf1bd4..b4aa20250301 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2636,14 +2636,14 @@ static void commit_planes_for_stream(struct dc *dc, top_pipe_to_program->stream_res.tg); } - if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) - dc->hwss.interdependent_update_lock(dc, context, true); - else - /* Lock the top pipe while updating plane addrs, since freesync requires - * plane addr update event triggers to be synchronized. - * top_pipe_to_program is expected to never be NULL - */ - dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); + if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) + dc->hwss.interdependent_update_lock(dc, context, true); + else + /* Lock the top pipe while updating plane addrs, since freesync requires + * plane addr update event triggers to be synchronized. + * top_pipe_to_program is expected to never be NULL + */ + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true); // Stream updates if (stream_update) @@ -2659,11 +2659,10 @@ static void commit_planes_for_stream(struct dc *dc, if (dc->hwss.program_front_end_for_ctx) dc->hwss.program_front_end_for_ctx(dc, context); - if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) - dc->hwss.interdependent_update_lock(dc, context, false); - else - dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); - + if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) + dc->hwss.interdependent_update_lock(dc, context, false); + else + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); dc->hwss.post_unlock_program_front_end(dc, context); return; } @@ -2764,6 +2763,7 @@ static void commit_planes_for_stream(struct dc *dc, plane_state->flip_immediate); } } + /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; @@ -2786,12 +2786,13 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.update_plane_addr(dc, pipe_ctx); } } + } - if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) - dc->hwss.interdependent_update_lock(dc, context, false); - else - dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); + if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock) + dc->hwss.interdependent_update_lock(dc, context, false); + else + dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { @@ -2837,8 +2838,8 @@ static void commit_planes_for_stream(struct dc *dc, pipe_ctx->plane_state->skip_manual_trigger) continue; - if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) - pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c index b0c9180b808f..e7c56df8f762 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c @@ -795,10 +795,10 @@ bool hubp21_program_surface_flip_and_addr( flip_regs.tmz_surface = address->tmz_surface; flip_regs.immediate = flip_immediate; - if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) - dmcub_PLAT_54186_wa(hubp, &flip_regs); - else - program_surface_flip_and_addr(hubp, &flip_regs); + if (hubp->ctx->dc->debug.enable_dmcub_surface_flip && address->type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) + dmcub_PLAT_54186_wa(hubp, &flip_regs); + else + program_surface_flip_and_addr(hubp, &flip_regs); hubp->request_address = *address; diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 9a3f2a44f882..7a3beaecd19d 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -264,7 +264,6 @@ static inline unsigned long long dm_get_timestamp(struct dc_context *ctx) unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx, unsigned long long current_time_stamp, unsigned long long last_time_stamp); - /* * performance tracing */ diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 3ef6b536ccea..deff333e7437 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -323,6 +323,7 @@ struct dmub_srv_hw_funcs { uint32_t (*get_gpint_response)(struct dmub_srv *dmub); + uint32_t (*get_current_time)(struct dmub_srv *dmub); }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index b11f530f682c..8cdc1c75394e 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -399,3 +399,8 @@ void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) boot_options.bits.skip_phy_init_panel_sequence = skip; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } + +uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h index 42d610a260ef..f772f8b348ea 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h @@ -107,7 +107,8 @@ struct dmub_srv; DMUB_SR(MMHUBBUB_SOFT_RESET) \ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ DMUB_SR(DCN_VM_FB_OFFSET) \ - DMUB_SR(DMCUB_INTERRUPT_ACK) + DMUB_SR(DMCUB_INTERRUPT_ACK) \ + DMUB_SR(DMCUB_TIMER_CURRENT) #define DMUB_COMMON_FIELDS() \ DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ @@ -231,4 +232,6 @@ bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub); bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub); +uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub); + #endif /* _DMUB_DCN20_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index ed9fa6138aa6..fa89ada1e313 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -159,6 +159,7 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; + funcs->get_current_time = dmub_dcn20_get_current_time; // Out mailbox register access functions for RN and above funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx