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Thu, 5 Aug 2021 03:32:19 -0500 From: Jingwen Chen To: CC: , , , Jingwen Chen , Jack Zhang Subject: [PATCHv2 2/2] drm/amd/amdgpu: add tdr support for embeded hw_fence Date: Thu, 5 Aug 2021 16:31:48 +0800 Message-ID: <20210805083146.324741-2-Jingwen.Chen2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210805083146.324741-1-Jingwen.Chen2@amd.com> References: <20210805083146.324741-1-Jingwen.Chen2@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0fd8495c-9b6b-4d88-ef27-08d957eb8bb4 X-MS-TrafficTypeDiagnostic: BN9PR12MB5292: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gfJ/EzB4cPW64NczARWMoLaQfFmJTcxQ2KK51kD8TxWm1fdpZdzS9x/EVo/3N3yp9t7HwotdvZWWj+FIhXur3Zwttk1Jhpagv7JZld+aTZh3LfhqcEjV6CxuhxQFtFyuoYzhDECBqv7DLP5tPqNw+jabhVv31ZJrSLVpKIci5uO9+k+Z58BDPOWE7//GAxrd7LIZ0sVY+41DIsmh4kl5QCDhAPtJ21FU3Mlq86FXAwZQrQDJ1bSKfHqRX5yYpaq7Tbn/+Hj2XYVnxCyVX8TRkckdXL4edtrzA6NRDDd1yJs9rRIXq+jD7UrU0uJuEOuVoQlEyE2La0D3Kls3hhTO/2l7odKL+vFU3GR9SmjQwHl1lURoMjHY+ehxK9hi6eiiMpQPJxKcQQy5yrvXmsMvb0Ar0vhyLbJkMSG4bICcFhG9B2kaAQ8TJEngMJR4uoye4Uq9N+Wtu1eIlssL+eDzbuXSbg0qhTQckj/lrhMa5Xkts8qstq56ORhEta69E2ZKxCecLU824F8SU0PApxUWHBEVuC8gcW+ihR42cMPaFsMxVNlrwoJg90rabU8BOMjdCBuCVfy0aS8yBh95eVJ02vw6BCI4vf0G8TSJa9S+9dUVnAQ78iRkonWrgSDQpR8TBqQOYrRaxy3w8mhx4jk9/tSqSHObmKTQ16SoA82OoA4kZGxDWm/IGpXm3AXPbxTzKwz1xDKjz6U2+fQbGQkOU/UUEsi8QeHuNMprZ6GfUgg= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(376002)(396003)(346002)(39860400002)(136003)(36840700001)(356005)(70206006)(426003)(1076003)(8676002)(86362001)(36860700001)(2616005)(7696005)(70586007)(6666004)(5660300002)(478600001)(82740400003)(8936002)(81166007)(2906002)(336012)(186003)(45080400002)(4326008)(316002)(32650700002)(36756003)(83380400001)(54906003)(26005)(82310400003)(6916009)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 08:32:22.1558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0fd8495c-9b6b-4d88-ef27-08d957eb8bb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5292 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [Why] After embeded hw_fence to amdgpu_job, we need to add tdr support for this feature. [How] 1. Add a resubmit_flag for resubmit jobs. 2. Clear job fence from RCU and force complete vm flush fences in pre_asic_reset 3. skip dma_fence_get for resubmit jobs and add a dma_fence_put for guilty jobs. v2: use a job_run_counter in amdgpu_job to replace the resubmit_flag in drm_sched_job. When the job_run_counter >= 1, it means this job is a resubmit job. Signed-off-by: Jack Zhang Signed-off-by: Jingwen Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +++ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 9e53ff851496..ade2fa07a50a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4447,7 +4447,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, struct amdgpu_reset_context *reset_context) { - int i, r = 0; + int i, j, r = 0; struct amdgpu_job *job = NULL; bool need_full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); @@ -4471,6 +4471,16 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, if (!ring || !ring->sched.thread) continue; + /*clear job fence from fence drv to avoid force_completion + *leave NULL and vm flush fence in fence drv */ + for (j = 0; j <= ring->fence_drv.num_fences_mask; j ++) { + struct dma_fence *old,**ptr; + ptr = &ring->fence_drv.fences[j]; + old = rcu_dereference_protected(*ptr, 1); + if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) { + RCU_INIT_POINTER(*ptr, NULL); + } + } /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ amdgpu_fence_driver_force_completion(ring); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 5e29d797a265..c9752cf794fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -159,10 +159,15 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd } seq = ++ring->fence_drv.sync_seq; - dma_fence_init(fence, &amdgpu_fence_ops, - &ring->fence_drv.lock, - adev->fence_context + ring->idx, - seq); + if (job != NULL && job->job_run_counter) { + /* reinit seq for resubmitted jobs */ + fence->seqno = seq; + } else { + dma_fence_init(fence, &amdgpu_fence_ops, + &ring->fence_drv.lock, + adev->fence_context + ring->idx, + seq); + } if (job != NULL) { /* mark this fence has a parent job */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 65a395060de2..19b13a65c73b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -254,6 +254,7 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */ if (finished->error < 0) { + dma_fence_put(&job->hw_fence); DRM_INFO("Skip scheduling IBs!\n"); } else { r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, @@ -262,7 +263,9 @@ static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job) DRM_ERROR("Error scheduling IBs (%d)\n", r); } - dma_fence_get(fence); + if (!job->job_run_counter) + dma_fence_get(fence); + job->job_run_counter ++; amdgpu_job_free_resources(job); fence = r ? ERR_PTR(r) : fence; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h index 92324c978534..1fa667f245e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -64,6 +64,9 @@ struct amdgpu_job { /* user fence handling */ uint64_t uf_addr; uint64_t uf_sequence; + + /* job_run_counter >= 1 means a resubmit job */ + uint32_t job_run_counter; }; int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, -- 2.25.1