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Fri, 24 Sep 2021 14:10:04 -0500 From: Anson Jacob To: CC: , , , , , , , , , , , , Wenjing Liu , Jun Lei Subject: [PATCH 11/24] drm/amd/display: add two lane settings training options Date: Fri, 24 Sep 2021 15:09:21 -0400 Message-ID: <20210924190934.1193379-12-Anson.Jacob@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210924190934.1193379-1-Anson.Jacob@amd.com> References: <20210924190934.1193379-1-Anson.Jacob@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 25e76c0e-0e49-407c-b727-08d97f8eed88 X-MS-TrafficTypeDiagnostic: CH2PR12MB3654: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WC9zkfUUu3TXowtgMpEPDWy6qcdi9/Uptq8JMWxcJzWK6I6Ls5jRxhNun1t2a6BmNr4BYkp946VAcKLXoFUeNd1eni+QDH9Iv8G2gPdT41O/tI/Tu2FcTlu5ejWaoCYtbUUeo72jrLUymfLjCJnGfcoXKjKUWk6wNCsEY6r3ORqh50QiYOnjkWysSoKdBH5EfE8W1gMg9eCRpE+cCLnxQIQie6wGTx4LLpP7slgedGp/zBb5aYWqvJyV6Bs6FaFBMdmg6ujj5pa3WGF1c/13U+Mjv9Dpc0eEV73+3bJ0iSOTIKDR25AM0pUKit3s92n6ObnHdA6CuEdJFynjfKnEmwRRfuKvzXRSCEkb5Ykmpsm0doIKkIxH6cbLPNpcjyqbrQLyo72Z88GqT3nHLhXr3AjjBsaOTr7ZpbhS37r0WszJVF8+M623R384svdqPZAwBMoAHA1mcsVMIdXc/mhfmNCi+GeGaq5qyIfeqCgoLfpS2+zRNKeQw/d6E+cznZsC4XRYnjpzLuF2YmfpHnHfy08DekerBzsq1FllDyXMgvpTx2Y9KBV1grz+bX66Sye4COuzzdZ0VRyuoI52xR+LiH0D02KfjYhDsX7qMKzm5I0fMciux0Q5drhC4yKjtgFkrEfQuLBN6dwwu9pcDLJwrBwKNbJs0IOMfYjxnNn8V5jfthluetVeK2WUFRjoey7vL+CCpcwbJ6ONBXWz4qvuVWaupGivngsIpT5tSLdYf/I= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(70206006)(5660300002)(316002)(4326008)(81166007)(2906002)(36756003)(36860700001)(356005)(6916009)(86362001)(47076005)(6666004)(8936002)(186003)(83380400001)(26005)(2616005)(426003)(1076003)(7696005)(8676002)(336012)(82310400003)(508600001)(70586007)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2021 19:10:09.5340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25e76c0e-0e49-407c-b727-08d97f8eed88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3654 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Wenjing Liu [why] option 1: disallow different lanes to have different lane settings option 2: dpcd lane settings will always use the same hw lane settings even if it doesn't match requested lane adjust Reviewed-by: Jun Lei Acked-by: Anson Jacob Signed-off-by: Wenjing Liu --- .../gpu/drm/amd/display/dc/core/dc_link_dp.c | 18 ++++++++++++------ .../amd/display/include/link_service_types.h | 6 +++++- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index f13bf8ca93aa..f55dac1c7ea1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -733,12 +733,16 @@ void dp_decide_lane_settings( #endif } - /* - * We find the maximum of the requested settings across all lanes - * and set this maximum for all lanes - */ - maximize_lane_settings(hw_lane_settings); dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings); + + if (lt_settings->disallow_per_lane_settings) { + /* we find the maximum of the requested settings across all lanes*/ + /* and set this maximum for all lanes*/ + maximize_lane_settings(hw_lane_settings); + if (lt_settings->always_match_dpcd_with_hw_lane_settings) + dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings); + } + } static uint8_t get_nibble_at_index(const uint8_t *buf, @@ -1455,6 +1459,8 @@ static inline void decide_8b_10b_training_settings( lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting); lt_settings->enhanced_framing = 1; lt_settings->should_set_fec_ready = true; + lt_settings->disallow_per_lane_settings = true; + lt_settings->always_match_dpcd_with_hw_lane_settings = true; dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); } @@ -1481,6 +1487,7 @@ static inline void decide_128b_132b_training_settings(struct dc_link *link, link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) * 20000; lt_settings->lttpr_mode = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ? LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT; + lt_settings->disallow_per_lane_settings = true; dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); } @@ -3593,7 +3600,6 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) dp_hw_to_dpcd_lane_settings(&link_training_settings, link_training_settings.hw_lane_settings, link_training_settings.dpcd_lane_settings); - link_training_settings.allow_invalid_msa_timing_param = false; /*Usage: Measure DP physical lane signal * by DP SI test equipment automatically. * PHY test pattern request is generated by equipment via HPD interrupt. diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 3fc868b19f2f..e94bcdb3e134 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -116,9 +116,13 @@ struct link_training_settings { #endif bool enhanced_framing; - bool allow_invalid_msa_timing_param; enum lttpr_mode lttpr_mode; + /* disallow different lanes to have different lane settings */ + bool disallow_per_lane_settings; + /* dpcd lane settings will always use the same hw lane settings + * even if it doesn't match requested lane adjust */ + bool always_match_dpcd_with_hw_lane_settings; /***************************************************************** * training states - parameters that can change in link training -- 2.25.1