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Fri, 24 Sep 2021 14:10:12 -0500 From: Anson Jacob To: CC: , , , , , , , , , , , , Oliver Logush , Charlene Liu , Jun Lei Subject: [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format Date: Fri, 24 Sep 2021 15:09:25 -0400 Message-ID: <20210924190934.1193379-16-Anson.Jacob@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210924190934.1193379-1-Anson.Jacob@amd.com> References: <20210924190934.1193379-1-Anson.Jacob@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eca5b292-43b5-4b01-a34b-08d97f8ef18c X-MS-TrafficTypeDiagnostic: CY4PR12MB1829: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:346; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: R74RVMLYR2JpPyXofvMMU3BbYI2hj06uRy5nDCW4Ob7ySkTOEGdZRD3OjFe49xMGhfPaFXZl+WqsDSlmhalWLMt4L+2sLzeTnnCoqcbOrliflJlbGM4LGkJ3dbxQmP6Oa1NxbQ8mt1A4ajrx6DoaUj/V3gpmkD5hQYU1VbubXQbWroIFSfIsZ6I8aR4O7uTUXVuWn5o880lmM4RFImgplLCwTN/lQYi9o6AQQ+u7fR4iy7B8f+cE3JuPPQxXtX9nrrXKfTP/fM+y/VYta1EWKm+8eqtue/sBJpkxnZCpjKmbWp4gOdyWPsYV+svNEgNqdQopyWybjN2SaWhl7DhmZoOAVdFId0mRQ45GRMLD8hoO2pqLYe6S8kYGjw+5AOveLqURlnu0+bwauEzp8soyCdjyW66MUcGMIO5OEY8XEfdJ6rDRKjbi21qGCOv+IM5ZP0LOjnHaYF2cnoquqIZ9QglUtgpyWR49RmHbYrLJsb5yYJo/6eNPJ5/hwjT+VVp9sIaqBHpfTYywRL286e0PwjPWox43Exaoyvsry8gGpQRSeNucfAz1vkDWBD6kPg+VsuAhFdsjP2EmmEP9aMbkPqbLrnMCvXVBXHZ13tauYd7bGzL2IqXXG5NQg5rbrGFiKjHuKsKiq2+zkhOcPSBxw7YX4a7s9yrzjrienSXL6iWixZF9FCnu+RU1pG7f3wG6u/xwhNEh9KD+3YkBRZz710wG0o4M0d74pzcbCHfcH1g= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(6916009)(8936002)(316002)(356005)(70586007)(70206006)(54906003)(47076005)(8676002)(7696005)(82310400003)(4326008)(2906002)(5660300002)(508600001)(2616005)(86362001)(36860700001)(36756003)(1076003)(426003)(336012)(186003)(6666004)(83380400001)(26005)(81166007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2021 19:10:16.3825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eca5b292-43b5-4b01-a34b-08d97f8ef18c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1829 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Oliver Logush Reviewed-by: Charlene Liu Reviewed-by: Jun Lei Acked-by: Anson Jacob Signed-off-by: Oliver Logush --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 6 ------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 1 - 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h index f0e0d07b0311..1ca4907b144d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h @@ -62,12 +62,6 @@ #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 #define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L -#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 -#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L -#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 -#define CURSOR2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L -#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 -#define CURSOR3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L #define IPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index 37848f4577b1..3d2a2848857a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -304,7 +304,7 @@ void optc1_program_timing( if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2) h_div = H_TIMING_DIV_BY2; - if (REG(OPTC_DATA_FORMAT_CONTROL)) { + if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { uint32_t data_fmt = 0; if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h index ec28cb9c3a8e..9ccbb2b519b7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h @@ -171,7 +171,6 @@ struct dwbc { bool dwb_is_efc_transition; bool dwb_is_drc; int wb_src_plane_inst;/*hubp, mpcc, inst*/ - bool update_privacymask; uint32_t mask_id; int otg_inst; bool mvc_cfg; -- 2.25.1