From: Solomon Chiu <solomon.chiu@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
<mikita.lipski@amd.com>, <roman.li@amd.com>,
<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
<solomon.chiu@amd.com>, Hansen <Hansen.Dsouza@amd.com>,
Charlene Liu <Charlene.Liu@amd.com>
Subject: [PATCH 09/14] drm/amd/display: Fix detection of 4 lane for DPALT
Date: Fri, 1 Oct 2021 22:36:15 +0800 [thread overview]
Message-ID: <20211001143620.192679-10-solomon.chiu@amd.com> (raw)
In-Reply-To: <20211001143620.192679-1-solomon.chiu@amd.com>
From: Hansen <Hansen.Dsouza@amd.com>
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
---
.../display/dc/dcn31/dcn31_dio_link_encoder.c | 33 ++++++++++++++++++-
.../display/dc/dcn31/dcn31_dio_link_encoder.h | 3 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
index 4f0a0803db6c..616a48d72afa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -63,6 +63,10 @@
#define AUX_REG_WRITE(reg_name, val) \
dm_write_reg(CTX, AUX_REG(reg_name), val)
+#ifndef MIN
+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
+#endif
+
void dcn31_link_encoder_set_dio_phy_mux(
struct link_encoder *enc,
enum encoder_type_select sel,
@@ -217,7 +221,7 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = {
.get_dig_frontend = dcn10_get_dig_frontend,
.get_dig_mode = dcn10_get_dig_mode,
.is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
- .get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+ .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
};
@@ -439,3 +443,30 @@ bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
return is_usb_c_alt_mode;
}
+
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings)
+{
+ struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+ uint32_t is_in_usb_c_dp4_mode = 0;
+
+ dcn10_link_encoder_get_max_link_cap(enc, link_settings);
+
+ /* in usb c dp2 mode, max lane count is 2 */
+ if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
+ if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
+ // [Note] no need to check hw_internal_rev once phy mux selection is ready
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ } else {
+ if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
+ || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
+ || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
+ REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ } else {
+ REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
+ }
+ }
+ if (!is_in_usb_c_dp4_mode)
+ link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
+ }
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
index bec50e4402ff..3454f1e7c1f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
@@ -252,4 +252,7 @@ void dcn31_link_encoder_disable_output(
bool dcn31_link_encoder_is_in_alt_mode(
struct link_encoder *enc);
+void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings);
+
#endif /* __DC_LINK_ENCODER__DCN31_H__ */
--
2.25.1
next prev parent reply other threads:[~2021-10-01 14:41 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 14:36 [PATCH 00/14] DC Patches October 1, 2021 Solomon Chiu
2021-10-01 14:36 ` [PATCH 01/14] drm/amd/display: Prevent using DMUB rptr that is out-of-bounds Solomon Chiu
2021-10-01 14:36 ` [PATCH 02/14] drm/amd/display: update irq_service and other required change part 2 Solomon Chiu
2021-10-01 14:36 ` [PATCH 03/14] drm/amd/display: Skip override for preferred link settings during link training Solomon Chiu
2021-10-01 14:36 ` [PATCH 04/14] drm/amd/display: Re-arrange FPU code structure for dcn2x Solomon Chiu
2021-10-01 14:36 ` [PATCH 05/14] drm/amd/display: Fix 3DLUT skipped programming Solomon Chiu
2021-10-01 14:36 ` [PATCH 06/14] drm/amd/display: dcn3 failed due to dmcbu_abm not created Solomon Chiu
2021-10-01 14:36 ` [PATCH 07/14] drm/amd/display: Added root clock optimization flags Solomon Chiu
2021-10-01 14:36 ` [PATCH 08/14] drm/amd/display: Limit display scaling to up to 4k for DCN 3.1 Solomon Chiu
2021-10-01 14:36 ` Solomon Chiu [this message]
2021-10-01 14:36 ` [PATCH 10/14] drm/amd/display: [FW Promotion] Release 0.0.87 Solomon Chiu
2021-10-01 14:36 ` [PATCH 11/14] drm/amd/display: 3.2.156 Solomon Chiu
2021-10-01 14:36 ` [PATCH 12/14] drm/amd/display: Add helper for blanking all dp displays Solomon Chiu
2021-10-01 14:36 ` [PATCH 13/14] drm/amd/display: Fix concurrent dynamic encoder assignment Solomon Chiu
2021-10-01 14:36 ` [PATCH 14/14] drm/amd/display: Fix error in dmesg at boot Solomon Chiu
2021-10-04 13:27 ` [PATCH 00/14] DC Patches October 1, 2021 Wheeler, Daniel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211001143620.192679-10-solomon.chiu@amd.com \
--to=solomon.chiu@amd.com \
--cc=Anson.Jacob@amd.com \
--cc=Aurabindo.Pillai@amd.com \
--cc=Bhawanpreet.Lakha@amd.com \
--cc=Charlene.Liu@amd.com \
--cc=Hansen.Dsouza@amd.com \
--cc=Harry.Wentland@amd.com \
--cc=Rodrigo.Siqueira@amd.com \
--cc=Sunpeng.Li@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=mikita.lipski@amd.com \
--cc=qingqing.zhuo@amd.com \
--cc=roman.li@amd.com \
--cc=stylon.wang@amd.com \
--cc=wayne.lin@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox