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Date: Fri, 1 Oct 2021 22:36:19 +0800 Message-ID: <20211001143620.192679-14-solomon.chiu@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211001143620.192679-1-solomon.chiu@amd.com> References: <20211001143620.192679-1-solomon.chiu@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 956365f9-a3e2-475a-c00f-08d984e9a0cf X-MS-TrafficTypeDiagnostic: MN2PR12MB2976: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Af9pBog5i73Nm6fwDqrb90hkXtRxT4haihMyR2WTB9g++Nb+u+eN+XrVasIwEFZIIcjXMAVKkYxT1hTOHSSyE5gW4tkhm6CoyCzjTRsZcHBIQpeDtzUTsEyULh3VKrFjO6uVRt1cOllIiE/Fi6JqLCwlW83UKReGMGUWe98rLfFsOkJMbBe08aZFPkRBTcSkqoVVBkcFkwZrK6y1F0J9RxIgEZ4PhnvBu9r5ntrpRXxWqF3hBA1M+em17hqR4EAsMGCHaOUawGPin/W6Pfi3i9Pr33Hk4+PdmkNHO+KBlHx9f81AoEf8hL9gZhSljDndbTp/686Si9xxNoqOPUY/sQbrgTVwz5yblKpy4nt3X6kbAWjxzgjMZHiEejrbT7mL6wI5ijt6N4xLePabfX3GHDySk+LeP+/HKbtglSWEgngumnIRZ6/hTksu3K4FAajkQLJyYULf8cOlwbvxiNZxOx9VM8uRytN1IQoBLjqcIDNPctzndNkugmIQ8A74DP84I/HC0LXjFyrMTX9uYE6GTOx3/fPUdwzUSWRw183TE2oYe/Zz7isCsgTNUqgeBXKkt7UtvLhdwlctyjIZs2nJ7DeXAcLAEHDtmnD0qppyYCzPh5nnqXhl9GXQ3bopwkTbAWXW6yxm21fs+wXR5fwU54gJYA4aRGty97nTsW0QDn3kPOIUxEfbN8+xIUtxWQDSP9D2Z05gnuw2CP2ivjgjAFsPi8ERPHpNmmn1eufUACs= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(6916009)(2906002)(83380400001)(8936002)(36756003)(82310400003)(316002)(1076003)(4326008)(54906003)(508600001)(36860700001)(44832011)(8676002)(7696005)(186003)(16526019)(47076005)(336012)(5660300002)(26005)(6666004)(86362001)(81166007)(356005)(426003)(70206006)(2616005)(70586007)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2021 14:42:00.7873 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 956365f9-a3e2-475a-c00f-08d984e9a0cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2976 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jimmy Kizito [Why] Trying to enable multiple displays simultaneously exposed shortcomings with the algorithm for dynamic link encoder assignment. The main problems were: - Assuming stream order remained constant across states would sometimes lead to invalid DIG encoder assignment. - Incorrect logic for deciding whether or not a DIG could support a stream would also sometimes lead to invalid DIG encoder assignment. - Changes in encoder assignment were wholesale while updating of the pipe backend is incremental. This would lead to the hardware state not matching the software state even with valid encoder assignments. [How] The following changes fix the identified problems. - Use stream pointer rather than stream index to track streams across states. - Fix DIG compatibility check by examining the link signal type rather than the stream signal type. - Modify assignment algorithm to make incremental updates so software and hardware states remain coherent. Additionally: - Add assertions and an encoder assignment validation function link_enc_cfg_validate() to detect potential problems with encoder assignment closer to their root cause. - Reduce the frequency with which the assignment algorithm is executed. It should not be necessary for fast state validation. Reviewed-by: Jun Lei Acked-by: Solomon Chiu Signed-off-by: Jimmy Kizito --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 74da226efffe..81bf1e5a64c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1926,9 +1926,9 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init) } if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) || - (!hw_init && dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) { - if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && - dc->links[i]->link_enc->funcs->get_dig_frontend) { + (!hw_init && dc->links[i]->link_enc && + dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) { + if (dc->links[i]->link_enc->funcs->get_dig_frontend) { fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc); if (fe == ENGINE_ID_UNKNOWN) continue; -- 2.25.1