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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2021 08:00:48.5053 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64131bab-510c-4e0c-7558-08d987d63e2c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1357 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jimmy Kizito [Why & How] Additional debug flags that can be useful for testing USB4 DP link training. Add flags: - 0x2 : Forces USB4 DP link to non-LTTPR mode - 0x4 : Extends status read intervals to about 60s. Reviewed-by: Meenakshikumar Somasundaram Reviewed-by: Jun Lei Acked-by: Wayne Lin Acked-by: Nicholas Kazlauskas Signed-off-by: Jimmy Kizito --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 ++++++ drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c | 6 ++++++ drivers/gpu/drm/amd/display/dc/dc.h | 4 +++- drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h | 3 +++ 4 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index bfba1d2c6a18..423fbd2b9b39 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -4528,6 +4528,12 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link) else link->lttpr_mode = LTTPR_MODE_NON_TRANSPARENT; } +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* Check DP tunnel LTTPR mode debug option. */ + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + link->dc->debug.dpia_debug.bits.force_non_lttpr) + link->lttpr_mode = LTTPR_MODE_NON_LTTPR; +#endif if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT || link->lttpr_mode == LTTPR_MODE_TRANSPARENT) { /* By reading LTTPR capability, RX assumes that we will enable diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c index 7407c755a73e..ce15a38c2aea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpia.c @@ -528,6 +528,12 @@ static uint32_t dpia_get_eq_aux_rd_interval(const struct dc_link *link, dp_translate_training_aux_read_interval( link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]); +#if defined(CONFIG_DRM_AMD_DC_DCN) + /* Check debug option for extending aux read interval. */ + if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval) + wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US; +#endif + return wait_time_microsec; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e3f884942e04..86fa94a2ef48 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -499,7 +499,9 @@ union root_clock_optimization_options { union dpia_debug_options { struct { uint32_t disable_dpia:1; - uint32_t reserved:31; + uint32_t force_non_lttpr:1; + uint32_t extend_aux_rd_interval:1; + uint32_t reserved:29; } bits; uint32_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h index 790b904e37e1..e3dfe4c89ce0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dpia.h @@ -34,6 +34,9 @@ struct dc_link_settings; /* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */ #define DPIA_CLK_SYNC_DELAY 16000 +/* Extend interval between training status checks for manual testing. */ +#define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000 + /** @note Can remove once DP tunneling registers in upstream include/drm/drm_dp_helper.h */ /* DPCD DP Tunneling over USB4 */ #define DP_TUNNELING_CAPABILITIES_SUPPORT 0xe000d -- 2.25.1