From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
<mikita.lipski@amd.com>, <roman.li@amd.com>,
<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
<solomon.chiu@amd.com>, <pavle.kotarac@amd.com>,
<agustin.gutierrez@amd.com>,
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
Aric Cyr <Aric.Cyr@amd.com>
Subject: [PATCH 19/33] drm/amd/display: allow windowed mpo + odm
Date: Sun, 24 Oct 2021 09:31:27 -0400 [thread overview]
Message-ID: <20211024133141.239861-20-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20211024133141.239861-1-Rodrigo.Siqueira@amd.com>
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
This change adds a config flag to allow non fullscreen MPO during ODM.
Scaling calculation will still fail configurations where video is only
one one side of the screen.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
---
.../gpu/drm/amd/display/dc/core/dc_resource.c | 14 +++++++--
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 30 ++++++++++---------
3 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9e83fd54e2ca..c32fdccd4d92 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1155,9 +1155,17 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
}
- if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
- pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
- res = false;
+ if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
+ if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
+ pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
+ res = false;
+ } else {
+ /* Clamp minimum viewport size */
+ if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
+ pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
+ if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
+ pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
+ }
DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
"src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1225406d3381..4cd26ca26fe0 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -323,6 +323,7 @@ struct dc_config {
bool multi_mon_pp_mclk_switch;
bool disable_dmcu;
bool enable_4to1MPC;
+ bool enable_windowed_mpo_odm;
bool allow_edp_hotplug_detection;
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool clamp_min_dcfclk;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 3a8a3214f770..6d70ccb108af 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -1929,23 +1929,25 @@ noinline bool dcn30_internal_validate_bw(
if (vlevel == context->bw_ctx.dml.soc.num_states)
goto validate_fail;
- for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
- struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
+ if (!dc->config.enable_windowed_mpo_odm) {
+ for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+ struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
+ struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
- if (!pipe->stream)
- continue;
+ if (!pipe->stream)
+ continue;
- /* We only support full screen mpo with ODM */
- if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
- && pipe->plane_state && mpo_pipe
- && memcmp(&mpo_pipe->plane_res.scl_data.recout,
- &pipe->plane_res.scl_data.recout,
- sizeof(struct rect)) != 0) {
- ASSERT(mpo_pipe->plane_state != pipe->plane_state);
- goto validate_fail;
+ /* We only support full screen mpo with ODM */
+ if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
+ && pipe->plane_state && mpo_pipe
+ && memcmp(&mpo_pipe->plane_res.scl_data.recout,
+ &pipe->plane_res.scl_data.recout,
+ sizeof(struct rect)) != 0) {
+ ASSERT(mpo_pipe->plane_state != pipe->plane_state);
+ goto validate_fail;
+ }
+ pipe_idx++;
}
- pipe_idx++;
}
/* merge pipes if necessary */
--
2.25.1
next prev parent reply other threads:[~2021-10-24 13:32 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-24 13:31 [PATCH 00/33] DC Patches October 24, 2020 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 01/33] drm/amd/display: Align bw context with hw config when system resume Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 02/33] drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 03/33] drm/amd/display: Get ceiling for v_total calc Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 04/33] drm/amd/display: dc_link_set_psr_allow_active refactoring Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 05/33] drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 06/33] drm/amd/display: move FPU associated DSC code to DML folder Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 07/33] drm/amd/display: fix a crash on USB4 over C20 PHY Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 08/33] drm/amd/display: Set i2c memory to light sleep during hw init Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 09/33] drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdate Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 10/33] drm/amd/display: clean up dcn31 revision check Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 11/33] drm/amd/display: restyle dcn31 resource header inline with other asics Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 12/33] drm/amd/display: Implement fixed DP drive settings Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 13/33] drm/amd/display: Add comment for preferred_training_settings Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 14/33] drm/amd/display: Handle I2C-over-AUX write channel status update Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 15/33] drm/amd/display: [FW Promotion] Release 0.0.89 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 16/33] drm/amd/display: 3.2.158 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 17/33] drm/amd/display: Fix 3DLUT skipped programming Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 18/33] drm/amd/display: set Layout properly for 8ch audio at timing validation Rodrigo Siqueira
2021-10-24 13:31 ` Rodrigo Siqueira [this message]
2021-10-24 13:31 ` [PATCH 20/33] drm/amd/display: Remove unused macros Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 21/33] drm/amd/display: [FW Promotion] Release 0.0.90 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 22/33] drm/amd/display: 3.2.159 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 23/33] drm/amd/display: Manually adjust strobe for DCN303 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 24/33] drm/amd/display: Set phy_mux_sel bit in dmub scratch register Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 25/33] drm/amd/display: Add workaround flag for EDID read on certain docks Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 26/33] drm/amd/display: FEC configuration for dpia links Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 27/33] drm/amd/display: FEC configuration for dpia links in MST mode Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 28/33] drm/amd/display: adopt DP2.0 LT SCR revision 8 Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 29/33] drm/amd/display: implement decide lane settings Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 30/33] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 31/33] drm/amd/display: add two lane settings training options Rodrigo Siqueira
2021-10-24 13:31 ` [PATCH 32/33] drm/amd/display: fix link training regression for 1 or 2 lane Rodrigo Siqueira
2021-10-25 11:25 ` Paul Menzel
2021-10-25 13:58 ` Harry Wentland
2021-10-25 14:42 ` Kazlauskas, Nicholas
2021-10-25 15:12 ` Paul Menzel
2021-10-25 15:25 ` Harry Wentland
2021-10-25 14:56 ` Rodrigo Siqueira Jordao
2021-10-24 13:31 ` [PATCH 33/33] drm/amd/display: move FPU associated DCN301 code to DML folder Rodrigo Siqueira
2021-10-25 13:07 ` [PATCH 00/33] DC Patches October 24, 2020 Wheeler, Daniel
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