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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36860700001)(82310400003)(86362001)(4326008)(426003)(336012)(70586007)(54906003)(6916009)(36756003)(2906002)(47076005)(70206006)(2616005)(8936002)(26005)(8676002)(508600001)(1076003)(16526019)(186003)(83380400001)(81166007)(356005)(5660300002)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2021 13:32:16.7317 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f617a72-9fd4-4537-8996-08d996f2b265 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1500 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Ahmad Othman [Why] Created new fields that matches new B0 structs On DCN31 the mapping of DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this new mapping needed to be handled. [How] Mapped new structure based on new structs Added logic for mapping over A0 and B0 boards Hooked all new structs together. Reviewed-by: Wenjing Liu Acked-by: Agustin Gutierrez Signed-off-by: Ahmad Othman --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 53 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dc.h | 13 +++-- drivers/gpu/drm/amd/display/dc/dm_cp_psp.h | 2 + .../drm/amd/display/modules/inc/mod_hdcp.h | 2 + 4 files changed, 64 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index dfec35caf426..42f96de496cb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3582,6 +3582,9 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; #if defined(CONFIG_DRM_AMD_DC_DCN) struct link_encoder *link_enc = NULL; + struct dc_state *state = pipe_ctx->stream->ctx->dc->current_state; + struct link_enc_assignment link_enc_assign; + int i; #endif if (cp_psp && cp_psp->funcs.update_stream_config) { @@ -3595,9 +3598,57 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst; #if defined(CONFIG_DRM_AMD_DC_DCN) config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; - if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY) { + + if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY || + pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { link_enc = pipe_ctx->stream->link->link_enc; + config.dio_output_type = pipe_ctx->stream->link->ep_type; + config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + // Initialize PHY ID with ABCDE - 01234 mapping except when it is B0 config.phy_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A; + + //look up the link_enc_assignment for the current pipe_ctx + for (i = 0; i < state->stream_count; i++) { + if (pipe_ctx->stream == state->streams[i]) { + link_enc_assign = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i]; + } + } + + if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0) + config.dig_be = link_enc_assign.eng_id; + + // Add RegKey to guard B0 implementation + if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 && link_enc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { + if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { + link_enc = pipe_ctx->stream->link->link_enc; + + // enum ID 1-4 maps to DPIA PHY ID 0-3 + config.phy_idx = link_enc_assign.ep_id.link_id.enum_id - ENUM_ID_1; + } else { // for non DPIA mode over B0, ABCDE maps to 01564 + + switch (link_enc->transmitter) { + case TRANSMITTER_UNIPHY_A: + config.phy_idx = 0; + break; + case TRANSMITTER_UNIPHY_B: + config.phy_idx = 1; + break; + case TRANSMITTER_UNIPHY_C: + config.phy_idx = 5; + break; + case TRANSMITTER_UNIPHY_D: + config.phy_idx = 6; + break; + case TRANSMITTER_UNIPHY_E: + config.phy_idx = 4; + break; + default: + config.phy_idx = 0; + break; + } + + } + } } else if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) { link_enc = link_enc_cfg_get_link_enc_used_by_stream( pipe_ctx->stream->ctx->dc, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f0141f27880f..23977de4811b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -211,12 +211,12 @@ struct dc_dcc_setting { unsigned int max_uncompressed_blk_size; bool independent_64b_blks; #if defined(CONFIG_DRM_AMD_DC_DCN) - //These bitfields to be used starting with DCN 3.0 + //These bitfields to be used starting with DCN struct { - uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) - uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 - uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 - uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) + uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) + uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN + uint32_t dcc_256_128_128 : 1; //available starting with DCN + uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) } dcc_controls; #endif }; @@ -731,6 +731,9 @@ struct dc { #if defined(CONFIG_DRM_AMD_DC_DCN) bool idle_optimizations_allowed; #endif +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool enable_c20_dtm_b0; +#endif /* Require to maintain clocks and bandwidth for UEFI enabled HW */ diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h index 43f33e186088..511f9e1159c7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h +++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h @@ -35,6 +35,8 @@ struct cp_psp_stream_config { uint8_t link_enc_idx; uint8_t stream_enc_idx; uint8_t phy_idx; + uint8_t dio_output_idx; + uint8_t dio_output_type; uint8_t assr_enabled; uint8_t mst_enabled; uint8_t dp2_enabled; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h index f37101f5a777..6d648c889866 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h @@ -249,6 +249,8 @@ struct mod_hdcp_link { uint8_t ddc_line; uint8_t link_enc_idx; uint8_t phy_idx; + uint8_t dio_output_type; + uint8_t dio_output_id; uint8_t hdcp_supported_informational; union { struct mod_hdcp_displayport dp; -- 2.25.1