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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(16526019)(2906002)(8676002)(508600001)(186003)(5660300002)(86362001)(47076005)(82310400003)(54906003)(26005)(36756003)(4326008)(70206006)(6666004)(1076003)(44832011)(83380400001)(426003)(316002)(2616005)(356005)(8936002)(70586007)(336012)(6916009)(81166007)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2021 14:09:34.3534 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22da17a5-aa3d-49f4-5d12-08d9a065e514 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5409 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alexander.deucher@amd.com, pierre-eric.pelloux-prayer@amd.com, Felix.Kuehling@amd.com, Nirmoy Das , Christian.Koenig@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Add HIQ ring structs and functions that will map HIQ using KIQ. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 142 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 24 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +- 4 files changed, 169 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h index 89e6ad30396f..2d9295adac06 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h @@ -40,6 +40,7 @@ struct amdgpu_doorbell { */ struct amdgpu_doorbell_index { uint32_t kiq; + uint32_t hiq; uint32_t mec_ring0; uint32_t mec_ring1; uint32_t mec_ring2; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 1916ec84dd71..5b8cb76e35a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -256,6 +256,148 @@ void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); } +int amdgpu_gfx_hiq_acquire(struct amdgpu_device *adev, struct amdgpu_ring *ring) +{ + int queue_bit; + int mec, pipe, queue; + + queue_bit = adev->gfx.mec.num_mec + * adev->gfx.mec.num_pipe_per_mec + * adev->gfx.mec.num_queue_per_pipe; + + while (queue_bit-- >= 0) { + if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) + continue; + + amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); + + if (mec == 1 && pipe > 1) + continue; + + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + return 0; + } + + dev_err(adev->dev, "Failed to find a queue for HIQ\n"); + return -EINVAL; +} + +int amdgpu_gfx_hiq_init_ring(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq) +{ + struct amdgpu_hiq *hiq = &adev->gfx.hiq; + int r = 0; + + ring->adev = NULL; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = adev->doorbell_index.hiq; + + r = amdgpu_gfx_hiq_acquire(adev, ring); + if (r) + return r; + + ring->eop_gpu_addr = hiq->eop_gpu_addr; + ring->no_scheduler = true; + sprintf(ring->name, "hiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); + r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, + AMDGPU_RING_PRIO_DEFAULT, NULL); + if (r) + dev_warn(adev->dev, "(%d) failed to init hiq ring\n", r); + + return r; +} + +void amdgpu_gfx_hiq_free_ring(struct amdgpu_ring *ring) +{ + amdgpu_ring_fini(ring); +} + +void amdgpu_gfx_hiq_init_ring_fini(struct amdgpu_device *adev) +{ + struct amdgpu_hiq *hiq = &adev->gfx.hiq; + + amdgpu_bo_free_kernel(&hiq->eop_obj, &hiq->eop_gpu_addr, NULL); +} + +int amdgpu_gfx_hiq_init(struct amdgpu_device *adev, + unsigned hpd_size) +{ + int r; + u32 *hpd; + struct amdgpu_hiq *hiq = &adev->gfx.hiq; + + r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &hiq->eop_obj, + &hiq->eop_gpu_addr, (void **)&hpd); + if (r) { + dev_warn(adev->dev, "failed to create HIQ bo (%d).\n", r); + return r; + } + + memset(hpd, 0, hpd_size); + + r = amdgpu_bo_reserve(hiq->eop_obj, true); + if (unlikely(r != 0)) + dev_warn(adev->dev, "(%d) reserve hiq eop bo failed\n", r); + amdgpu_bo_kunmap(hiq->eop_obj); + amdgpu_bo_unreserve(hiq->eop_obj); + + return 0; +} + +int amdgpu_gfx_disable_hiq(struct amdgpu_device *adev) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + struct amdgpu_ring *kiq_ring = &kiq->ring; + int r; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock(&adev->gfx.kiq.ring_lock); + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock(&adev->gfx.kiq.ring_lock); + return -ENOMEM; + } + + kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.kiq.ring, RESET_QUEUES, + 0, 0); + r = amdgpu_ring_test_helper(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + + return r; +} + +int amdgpu_gfx_enable_hiq(struct amdgpu_device *adev) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *hiq_ring = &adev->gfx.hiq.ring; + int r; + + spin_lock(&adev->gfx.kiq.ring_lock); + r = amdgpu_ring_alloc(kiq_ring, 7); + if (r) { + pr_err("Failed to alloc KIQ (%d).\n", r); + return r; + } + + kiq->pmf->kiq_map_queues(kiq_ring, hiq_ring); + amdgpu_ring_commit(kiq_ring); + r = amdgpu_ring_test_helper(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + if (r) + DRM_ERROR("HIQ enable failed\n"); + + return r; + + } + static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, struct amdgpu_ring *ring) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index f851196c83a5..4d9c91f4400d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -111,6 +111,20 @@ struct amdgpu_kiq { const struct kiq_pm4_funcs *pmf; }; +/* + * Because of a HW bug HIQ need to be mapped so that CP can handle + * TMZ buffers. amdgpu is not going to use HIQ in any way other than + * mapping it using KIQ. KFD will map HIQ as well, so when KFD is enabled + * then amdgpu don't need to map HIQ. + */ + +struct amdgpu_hiq { + u64 eop_gpu_addr; + struct amdgpu_bo *eop_obj; + struct amdgpu_ring ring; + struct amdgpu_irq_src irq; +}; + /* * GPU scratch registers structures, functions & helpers */ @@ -275,6 +289,7 @@ struct amdgpu_gfx { struct amdgpu_me me; struct amdgpu_mec mec; struct amdgpu_kiq kiq; + struct amdgpu_hiq hiq; struct amdgpu_scratch scratch; const struct firmware *me_fw; /* ME firmware */ uint32_t me_fw_version; @@ -411,4 +426,13 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state); + +int amdgpu_gfx_hiq_init_ring(struct amdgpu_device *adev, + struct amdgpu_ring *ring, + struct amdgpu_irq_src *irq); +void amdgpu_gfx_hiq_free_ring(struct amdgpu_ring *ring); +void amdgpu_gfx_hiq_fini(struct amdgpu_device *adev); +int amdgpu_gfx_hiq_init(struct amdgpu_device *adev, unsigned int hpd_size); +int amdgpu_gfx_enable_hiq(struct amdgpu_device *adev); +int amdgpu_gfx_disable_hiq(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 4d380e79752c..438ed4ab86b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -71,7 +71,8 @@ enum amdgpu_ring_type { AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, AMDGPU_RING_TYPE_KIQ, - AMDGPU_RING_TYPE_MES + AMDGPU_RING_TYPE_MES, + AMDGPU_RING_TYPE_HIQ }; enum amdgpu_ib_pool_type { -- 2.31.1