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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 21:30:00.5292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddbc9d51-f3d9-42b9-5489-08da295e404e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5283 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Likun Gao , Hawking Zhang Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Hawking Zhang To match with smu v13_0_0 Signed-off-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index d516de41e6a9..ae8f6d299ed9 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1806,6 +1806,130 @@ struct atom_smu_info_v3_3 { uint32_t reserved; }; +struct atom_smu_info_v3_6 +{ + struct atom_common_table_header table_header; + uint8_t smuip_min_ver; + uint8_t smuip_max_ver; + uint8_t waflclk_ss_mode; + uint8_t gpuclk_ss_mode; + uint16_t sclk_ss_percentage; + uint16_t sclk_ss_rate_10hz; + uint16_t gpuclk_ss_percentage; + uint16_t gpuclk_ss_rate_10hz; + uint32_t core_refclk_10khz; + uint32_t syspll0_1_vco_freq_10khz; + uint32_t syspll0_2_vco_freq_10khz; + uint8_t pcc_gpio_bit; + uint8_t pcc_gpio_polarity; + uint16_t smugoldenoffset; + uint32_t syspll0_0_vco_freq_10khz; + uint32_t bootup_smnclk_10khz; + uint32_t bootup_socclk_10khz; + uint32_t bootup_mp0clk_10khz; + uint32_t bootup_mp1clk_10khz; + uint32_t bootup_lclk_10khz; + uint32_t bootup_dxioclk_10khz; + uint32_t ctf_threshold_override_value; + uint32_t syspll3_0_vco_freq_10khz; + uint32_t syspll3_1_vco_freq_10khz; + uint32_t bootup_fclk_10khz; + uint32_t bootup_waflclk_10khz; + uint32_t smu_info_caps; + uint16_t waflclk_ss_percentage; + uint16_t smuinitoffset; + uint32_t bootup_gfxavsclk_10khz; + uint32_t bootup_mpioclk_10khz; + uint32_t smb_slave_address; + uint32_t cg_fdo_ctrl0_val; + uint32_t cg_fdo_ctrl1_val; + uint32_t cg_fdo_ctrl2_val; + uint32_t gdfll_as_wait_ctrl_val; + uint32_t gdfll_as_step_ctrl_val; + uint32_t reserved_clk; + uint32_t fclk_syspll_refclk_10khz; + uint32_t smusvi_svc0_val; + uint32_t smusvi_svc1_val; + uint32_t smusvi_svd0_val; + uint32_t smusvi_svd1_val; + uint32_t smusvi_svt0_val; + uint32_t smusvi_svt1_val; + uint32_t cg_tach_ctrl_val; + uint32_t cg_pump_ctrl1_val; + uint32_t cg_pump_tach_ctrl_val; + uint32_t thm_ctf_delay_val; + uint32_t thm_thermal_int_ctrl_val; + uint32_t thm_tmon_config_val; + uint32_t bootup_vclk_10khz; + uint32_t bootup_dclk_10khz; + uint32_t smu_gpiopad_pu_en_val; + uint32_t smu_gpiopad_pd_en_val; + uint32_t reserved[12]; +}; + +struct atom_smu_info_v4_0 { + struct atom_common_table_header table_header; + uint32_t bootup_gfxclk_bypass_10khz; + uint32_t bootup_usrclk_10khz; + uint32_t bootup_csrclk_10khz; + uint32_t core_refclk_10khz; + uint32_t syspll1_vco_freq_10khz; + uint32_t syspll2_vco_freq_10khz; + uint8_t pcc_gpio_bit; + uint8_t pcc_gpio_polarity; + uint16_t bootup_vddusr_mv; + uint32_t syspll0_vco_freq_10khz; + uint32_t bootup_smnclk_10khz; + uint32_t bootup_socclk_10khz; + uint32_t bootup_mp0clk_10khz; + uint32_t bootup_mp1clk_10khz; + uint32_t bootup_lclk_10khz; + uint32_t bootup_dcefclk_10khz; + uint32_t ctf_threshold_override_value; + uint32_t syspll3_vco_freq_10khz; + uint32_t mm_syspll_vco_freq_10khz; + uint32_t bootup_fclk_10khz; + uint32_t bootup_waflclk_10khz; + uint32_t smu_info_caps; + uint16_t waflclk_ss_percentage; + uint16_t smuinitoffset; + uint32_t bootup_dprefclk_10khz; + uint32_t bootup_usbclk_10khz; + uint32_t smb_slave_address; + uint32_t cg_fdo_ctrl0_val; + uint32_t cg_fdo_ctrl1_val; + uint32_t cg_fdo_ctrl2_val; + uint32_t gdfll_as_wait_ctrl_val; + uint32_t gdfll_as_step_ctrl_val; + uint32_t bootup_dtbclk_10khz; + uint32_t fclk_syspll_refclk_10khz; + uint32_t smusvi_svc0_val; + uint32_t smusvi_svc1_val; + uint32_t smusvi_svd0_val; + uint32_t smusvi_svd1_val; + uint32_t smusvi_svt0_val; + uint32_t smusvi_svt1_val; + uint32_t cg_tach_ctrl_val; + uint32_t cg_pump_ctrl1_val; + uint32_t cg_pump_tach_ctrl_val; + uint32_t thm_ctf_delay_val; + uint32_t thm_thermal_int_ctrl_val; + uint32_t thm_tmon_config_val; + uint32_t smbus_timing_cntrl0_val; + uint32_t smbus_timing_cntrl1_val; + uint32_t smbus_timing_cntrl2_val; + uint32_t pwr_disp_timer_global_control_val; + uint32_t bootup_mpioclk_10khz; + uint32_t bootup_dclk0_10khz; + uint32_t bootup_vclk0_10khz; + uint32_t bootup_dclk1_10khz; + uint32_t bootup_vclk1_10khz; + uint32_t bootup_baco400clk_10khz; + uint32_t bootup_baco1200clk_bypass_10khz; + uint32_t bootup_baco700clk_bypass_10khz; + uint32_t reserved[16]; +}; + /* *************************************************************************** Data Table smc_dpm_info structure -- 2.35.1